Non-Posted transactions with no payload (memory read
requests, I/O read requests, Configuration read requests) are transferred across the RQ
interface in the same manner as a memory write request, except that the AXI4-Stream packet contains only the 16-byte descriptor. The following timing
diagrams in illustrate the transfer of a memory read request across the RQ interface, when the
interface width is configured as 64, 128, and 256 bits, respectively. The packet occupies two
consecutive beats on the 64-bit interface, while it is transferred in a single beat on the
128- and 256-bit interfaces. The s_axis_rq_tvalid signal must remain asserted
over the duration of the packet. The integrated block can deassert
s_axis_rq_tready to prolong the beat. The s_axis_rq_tlast
signal must be set in the last beat of the packet, and the bits in
s_axis_rq_tkeep[7:0] must be set in all Dword positions where a descriptor
is present.
The valid bytes in the first and last Dwords of the data
block to be read must be indicated using first_be[3:0] and
last_be[3:0], respectively. For the special case of a zero-length memory
read, the length of the request must be set to one Dword, with both
first_be[3:0] and last_be[3:0] set to all 0s. For memory
writes and reads of one DW transfers, last_be[3:0] should be 0s and bits in
first_be[3:0] indicate the valid bytes. Additionally when in
address-aligned mode, addr_offset[2:0] in s_axis_rq_tuser
specifies the desired starting alignment of data returned on the Requester Completion
interface. The alignment is not required to be correlated to the address of the request.