The timing diagrams in This Figure , This Figure , and This Figure illustrate the transfer of a Completion TLP received from the link with no associated payload across the RC interface, when the interface width is configured as 64, 128, and 256 bits, respectively. The timing diagrams in this section assume that the Completions are not straddled on the 256-bit interface. The straddle feature is described in Straddle Option for 256-Bit Interface .
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The entire transfer of the Completion TLP takes only a single beat on the 256- and 128-bit interfaces, and two beats on the 64-bit interface. The integrated block keeps the m_axis_rc_tvalid signal asserted over the duration of the packet. The user application can prolong a beat at any time by deasserting m_axis_rc_tready . The AXI4-Stream interface signals m_axis_rc_tkeep (one per Dword position) indicate the valid descriptor Dwords in the packet. That is, the tkeep bits are set to 1 contiguously from the first Dword of the descriptor until its last Dword. During the transfer of a packet, the tkeep bits can be 0 only in the last beat of the packet. The m_axis_rc_tlast signal is always asserted in the last beat of the packet.
The m_axi_rc_tuser bus also includes an is_sof_0 signal, which is asserted in the first beat of every packet. The user application can optionally use this signal to qualify the start of the descriptor on the interface. No other signals within m_axi_rc_tuser are relevant to the transfer of Completions with no data, when the straddle option is not in use.