The integrated block does not change the order of requests received from the user application on its requester interface when it transmits them on the link. In cases where the user application would like to have precise control of the order of transactions sent on the RQ interface and the CC interface (typically to avoid Completions from passing Posted requests when using strict ordering), the integrated block provides a mechanism for the user application to monitor the progress of a Posted transaction through its pipeline, so that it can determine when to schedule a Completion on the completer completion interface without the risk of passing a specific Posted request transmitted from the requester request interface,
When transferring a Posted request (memory write transactions or messages) across the requester request interface, the user application can provide an optional 4-bit sequence number to the integrated block on its seq_num[3:0] input within s_axis_rq_tuser . The sequence number must be valid in the first beat of the packet. The user application can then monitor the pcie_rq_seq_num[3:0] output of the core for this sequence number to appear. When the transaction has reached a stage in the internal transmit pipeline of the integrated block where a Completion cannot pass it, the integrated block asserts pcie_rq_seq_num_valid for one cycle and provides the sequence number of the Posted request on the pcie_rq_seq_num[3:0] output. Any Completions transmitted by the integrated block after the sequence number has appeared on pcie_rq_seq_num[3:0] cannot pass the Posted request in the internal transmit pipeline.