The timing diagrams in This Figure , This Figure , and This Figure illustrate the Dword-aligned transfer of a Completion TLP received from the link with an associated payload across the RC interface, when the interface width is configured as 64, 128, and 256 bits, respectively. For illustration purposes, the size of the data block being written into user application memory is assumed to be n Dwords, for some n = k × 32 + 28, k > 0. The timing diagrams in this section assume that the Completions are not straddled on the 256-bit interface. The straddle feature is described in Straddle Option for 256-Bit Interface .
In the Dword-aligned mode, the transfer starts with the three descriptor Dwords, followed immediately by the payload Dwords. The entire TLP, consisting of the descriptor and payload, is transferred as a single AXI4-Stream packet. Data within the payload is always a contiguous stream of bytes when the length of the payload exceeds two Dwords. The positions of the first valid byte within the first Dword of the payload and the last valid byte in the last Dword can then be determined from the Lower Address and Byte Count fields of the Request Completion Descriptor. When the payload size is two Dwords or less, the valid bytes in the payload cannot be contiguous. In these cases, the user application must store the First Byte Enable and the Last Byte Enable fields associated with each request sent out on the RQ interface and use them to determine the valid bytes in the completion payload. The user application can optionally use the byte enable outputs byte_en[31:0] within the m_axi_rc_tuser bus to determine the valid bytes in the payload, in the cases of contiguous as well as non-contiguous payloads.
The integrated block keeps the m_axis_rc_tvalid signal asserted over the entire duration of the packet. The user application can prolong a beat at any time by deasserting m_axis_rc_tready . The AXI4-Stream interface signals m_axis_rc_tkeep (one per Dword position) indicate the valid Dwords in the packet including the descriptor and any null bytes inserted between the descriptor and the payload. That is, the tkeep bits are set to 1 contiguously from the first Dword of the descriptor until the last Dword of the payload. During the transfer of a packet, the tkeep bits can be 0 only in the last beat of the packet, when the packet does not fill the entire width of the interface. The m_axis_rc_tlast signal is always asserted in the last beat of the packet.
The m_axi_rc_tuser bus provides several informational signals that can be used to simplify the logic associated with the user application side of the interface, or to support additional features. The is_sof_0 signal is asserted in the first beat of every packet, when its descriptor is on the bus. The byte enable outputs byte_en[31:0] (one per byte lane) indicate the valid bytes in the payload. These signals are asserted only when a valid payload byte is in the corresponding lane (it is not asserted for descriptor or null bytes). The asserted byte enable bits are always contiguous from the start of the payload, except when payload size is 2 Dwords or less. For Completion payloads of two Dwords or less, the 1s on byte_en might not be contiguous. Another special case is that of a zero-length memory read, when the integrated block transfers a one-Dword payload with the byte_en bits all set to 0. Thus, the user logic can, in all cases, use the byte_en signals directly to enable the writing of the associated bytes into memory.
The is_sof_1 , is_eof_0[3:0] , and is_eof_1[3:0] signals within the m_axis_rc_tuser bus are not to be used for 64-bit and 128-bit interfaces, and for 256-bit interfaces when the straddle option is not enabled.
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The timing diagrams in This Figure , This Figure , and This Figure illustrate the address-aligned transfer of a Completion TLP received from the link with an associated payload across the RC interface, when the interface width is configured as 64, 128, and 256 bits, respectively. In the example timing diagrams, the starting Dword address of the data block being transferred (as conveyed in bits [6:2] of the Lower Address field of the descriptor) is assumed to be ( m × 8 + 1), for an integer m . The size of the data block is assumed to be n Dwords, for some n = k × 32 + 28, k > 0. The straddle option is not valid for address-aligned transfers, so the timing diagrams assume that the Completions are not straddled on the 256-bit interface.
In the address-aligned mode, the delivery of the payload always starts in the beat following the last byte of the descriptor. The first byte of the payload can appear on any byte lane, based on the address of the first valid byte of the payload. The tkeep bits are set to 1 contiguously from the first Dword of the descriptor until the last Dword of the payload. The alignment of the first Dword on the data bus is determined by the setting of the addr_offset[2:0] input of the requester request interface when the user application sent the request to the integrated block. The user application can optionally use the byte enable outputs byte_en[31:0] to determine the valid bytes in the payload.
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