• High-performance, highly flexible, scalable, and reliable general-purpose I/O core
• Separate Requestor and Completer interfaces simplify design and increase performance
• Endpoint or Root Port configuration
• Multiple Function and Single-Root I/O Virtualization in the Endpoint configuration
• Compliant with PCI and PCI Express power management functions
• Optional Tag Management feature
• Maximum Payload Size (MPS) of up to 1024 bytes
• End-to-End Cyclic Redundancy Check (ECRC)
• Advanced Error Reporting (AER)
• Multi-Vector MSI up to 32 vectors
• MSI-X
• Atomic operations and (transaction layer packets) TLP processing hints
For a full list of features, see Feature Summary .
|
LogiCORE ™ IP Facts Table |
|||||
|---|---|---|---|---|---|
|
Core Specifics |
|||||
|
Supported Device Family (1) |
AMD UltraScale ™ Devices |
||||
|
Supported User Interfaces |
AXI4-Stream |
||||
|
Resources |
|||||
|
Provided with Core |
|||||
|
Design Files |
Verilog |
||||
|
Example Design |
Verilog |
||||
|
Test Bench |
Verilog |
||||
|
Constraints File |
XDC |
||||
|
Simulation Model |
Verilog |
||||
|
Supported
|
Root Port Driver |
||||
|
Tested Design Flows (2) |
|||||
|
Design Entry |
Vivado ™ Design Suite |
||||
|
Simulation |
For supported simulators, see t he Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
||||
|
Synthesis |
Vivado synthesis |
||||
|
Support |
|||||
|
Release Notes and Known Issues |
|||||
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
||||
|
Notes:
1.
For a complete list of supported devices, see the Vivado
2. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing . |
|||||