CORE CLOCK Frequency - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

This parameter allows you to select the core clock frequencies.

For Gen3 link speed:

The values of 250 MHz and 500 MHz are available for selection for speed grades -1, -2, -3, -1H and -1HV, and for a link width other than x8. For this configuration, this parameter is available when Advanced mode is selected.

For speed grades -1, -2, -3, -1H and -1HV, and for a link width of x8, this parameter defaults to 500 MHz and is not available for selection.

For a -1L or -1LV speed grade and a link width other than x8, this parameter defaults to 250 MHz and is not available for selection.

For Gen1 and Gen2 link speeds:

This parameter defaults to 250 MHz and is not available for selection.

Note: When a -1L or -1LV speed grade is selected, and non production parts of XCVU440 (ES2), XCKU060 (ES2) and XCKU115 (ES2) is selected, this parameter defaults to 250 MHz and is not available for selection.