Configuration Status Interface - 4.4 English

cfg_phy_link_down

Output

1

Configuration Link Down

Status of the PCI Express link based on the Physical Layer LTSSM.

1b: Link is Down (LinkUp state variable is 0b)

0b: Link is Up (LinkUp state variable is 1b )

Note: Per the PCI Express Base Specification, rev. 3.0 [Ref 2] , LinkUp is 1b in the Recovery, L0, L0s, L1, and L2 cfg_ltssm states. In the Configuration state, LinkUp can be 0b or 1b . It is always 0b when the Configuration state is reached using Detect > Polling > Configuration . LinkUp is 1b if the configuration state is reached through any other state transition.

Note: While reset is asserted, the output of this signal are 0b until reset is released.

cfg_phy_link_status

Output

2

Configuration Link Status

Status of the PCI Express link.

00b: No receivers detected

01b: Link training in progress

10b: Link up, DL initialization in progress

11b: Link up, DL initialization completed

cfg_negotiated_width

Output

4

Configuration Link Status.

Negotiated Link Width: PCI Express Link Status register, Negotiated Link Width field. This field output indicates the negotiated width of the given PCI Express Link and is valid when cfg_phy_link_status[1:0] == 11b (DL Initialization is complete).

Negotiated Link Width values:

• 0001b = x1

• 0010b = x2

• 0100b = x4

• 1000b = x8

Other values are reserved.

cfg_current_speed

Output

3

Current Link Speed

This signal outputs the current link speed from Link Status register bits 1 down to 0. This field indicates the negotiated Link speed of the given PCI Express Link.

• 001b: 2.5 GT/s PCI Express Link

• 010b: 5.0 GT/s PCI Express Link

• 100b: 8.0 GT/s PCI Express Link

Other values are reserved

cfg_max_payload

Output

3

Max_Payload_Size

This signal outputs the maximum payload size from Device Control register bits 7 down to 5. This field sets the maximum TLP payload size. As a Receiver, the logic must handle TLPs as large as the set value. As a Transmitter, the logic must not generate TLPs exceeding the set value.

000b: 128 bytes maximum payload size

001b: 256 bytes maximum payload size

010b: 512 bytes maximum payload size

• 011b: 1024 bytes maximum payload size

Other values are reserved

cfg_max_read_req

Output

3

Max_Read_Request_Size

This signal outputs the maximum read request size from Device Control register bits 14 down to 12. This field sets the maximum Read Request size for the logic as a Requester. The logic must not generate Read Requests with size exceeding the set value.

000b: 128 bytes maximum Read Request size

001b: 256 bytes maximum Read Request size

010b: 512 bytes maximum Read Request size

011b: 1024 bytes maximum Read Request size

100b: 2048 bytes maximum Read Request size

101b: 4096 bytes maximum Read Request size

Other values are reserved

cfg_function_status

Output

16

Configuration Function Status

These outputs indicate the states of the Command register bits in the PCI configuration space of each function. These outputs are used to enable requests and completions from the host logic. The assignment of bits is as follows:

Bit 0: Function 0 I/O Space Enable

Bit 1: Function 0 Memory Space Enable

Bit 2: Function 0 Bus Master Enable

Bit 3: Function 0 INTx Disable

Bit 4: Function 1 I/O Space Enable

Bit 5: Function 1 Memory Space Enable

Bit 6: Function 1 Bus Master Enable

• Bit 7: Function 1 INTx Disable

Bits [15:8] are reserved

cfg_vf_status

Output

16

Configuration Virtual Function Status

These outputs indicate the status of virtual functions, two bits each per virtual function.

Bit 0: Virtual function 0: Configured/Enabled by the software

Bit 1: Virtual function 0: PCI Command register, Bus Master Enable

Bits [15:12] are reserved.

cfg_function_power_state

Output

12

Configuration Function Power State

These outputs indicate the current power state of the physical functions. Bits [2:0] capture the power state of function 0, and bits [5:3] capture that of function 1, and so on. Bits [11:6] are reserved. The possible power states are:

000: D0_uninitialized

001: D0_active

010: D1

100: D3_hot

Other values are reserved.

cfg_vf_power_state

Output

24

Configuration Virtual Function Power State

These outputs indicate the current power state of the virtual functions. Bits [2:0] capture the power state of virtual function 0, and bits [5:3] capture that of virtual function 1, and so on. Bits [23:18] are reserved. The possible power states are:

000: D0_uninitialized

001: D0_active

010: D1

100: D3_hot

Other values are reserved.

cfg_link_power_state

Output

2

Current power state of the PCI Express link.

00: L0

01: L0s

10: L1

11: L2 (Note: L2 state is not supported)

cfg_err_cor_out

Output

1

Correctable Error Detected

In Endpoint mode, the core activates this output for one cycle when it has detected a correctable error and its reporting is not masked. In a multi-function Endpoint, this is the logical OR of the correctable error status bits in the Device Status registers of all functions.

In Root Port mode, this output is activated on detection of a local correctable error, when its reporting is not masked. This output does not respond to any errors signaled by remote devices using PCI Express error messages. These error messages are delivered through the message interface.

Note: This signal is not reliable when the user clk and core clk are different.

cfg_err_nonfatal_out

Output

1

Non-Fatal Error Detected

In Endpoint mode, the core activates this output for one cycle when it has detected a non-fatal error and its reporting is not masked. In a multi-function Endpoint, this is the logical OR of the non-fatal error status bits in the Device Status registers of all functions.

In Root Port mode, this output is activated on detection of a local non-fatal error, when its reporting is not masked. This output does not respond to any errors signaled by remote devices using PCI Express error messages. These error messages are delivered through the message interface.

Note: This status output might not be reliable for all Link/Speed configurations.

cfg_err_fatal_out

Output

1

Fatal Error Detected

In Endpoint mode, the core activates this output for one cycle when it has detected a fatal error and its reporting is not masked. In a multi-function Endpoint, this is the logical OR of the fatal error status bits in the Device Status registers of all functions.

In Root Port mode, this output is activated on detection of a local fatal error, when its reporting is not masked. This output does not respond to any errors signaled by remote devices using PCI Express error messages. These error messages are delivered through the message interface.

Note: This status output might not be reliable for all Link/Speed configurations.

cfg_ltr_enable

Output

1

Latency Tolerance Reporting Enable.

The state of this output reflects the setting of the LTR Mechanism Enable bit in the Device Control 2 register of physical function 0. When the core is configured as an Endpoint, the logic uses this output to enable the generation of LTR messages. This output is not to be used when the core is configured as a Root Port.

pcie_rq_tag_av

Output

2

Transmit flow control tag available, 1 if 1 or more tags are available

pcie_tfc_nph_av

Output

2

Transmit flow control non posted header credits available

00 - 0 or less credits available
01 - 1 credit available
10 - 2 credits available
11 - 3 or more credits available

cfg_ltssm_state

Output

6

LTSSM State. Shows the current LTSSM state:

00: Detect.Quiet
01: Detect.Active
02: Polling.Active
03: Polling.Compliance
04: Polling.Configuration
05: Configuration.Linkwidth.Start
06: Configuration.Linkwidth.Accept
07: Configuration.Lanenum.Accept
08: Configuration.Lanenum.Wait
09: Configuration.Complete
0A: Configuration.Idle
0B: Recovery.RcvrLock
0C: Recovery.Speed
0D: Recovery.RcvrCfg
0E: Recovery.Idle
10: L0
11: Rx_L0s.Entry

12: Rx_L0s.Idle

13: Rx_L0s.FTS

14: Tx_L0s.Entry

15: Tx_L0s.Idle

16: Tx_L0s.FTS

19: L2.Idle

1A: L2.TransmitWake

20: Disabled

21: Loopback_Entry_Master

22: Loopback_Active_Master

23: Loopback_Exit_Master

24: Loopback_Entry_Slave

25: Loopback_Active_Slave

26: Loopback_Exit_Slave

27: Hot_Reset

28: Recovery_Equalization_Phase0

29: Recovery_Equalization_Phase1

2a: Recovery_Equalization_Phase2

2b: Recovery_Equalization_Phase3

cfg_rcb_status

Output

4

RCB Status.

Provides the setting of the Read Completion Boundary (RCB) bit in the Link Control register of each physical function. In Endpoint mode, bit 0 indicates the RCB for Physical Function 0 (PF 0), bit 1 indicates the RCB for PF 1, and so on. In RC mode, bit 0 indicates the RCB setting of the Link Control register of the RP, bit 1 is reserved.

For each bit, a value of 0 indicates an RCB of 64 bytes and a value of 1 indicates 128 bytes.

cfg_pl_status_change

Output

1

This output is used by the core in Root Port mode to signal one of the following link training-related events:

(a) The link bandwidth changed as a result of the change in the link width or operating speed and the change was initiated locally (not by the link partner), without the link going down. This interrupt is enabled by the Link Bandwidth Management Interrupt Enable bit in the Link Control register. The status of this interrupt can be read from the Link Bandwidth Management Status bit of the Link Status register; or

(b) The link bandwidth changed autonomously as a result of the change in the link width or operating speed and the change was initiated by the remote node. This interrupt is enabled by the Link Autonomous Bandwidth Interrupt Enable bit in the Link Control register. The status of this interrupt can be read from the Link Autonomous Bandwidth Status bit of the Link Status register; or

(c) The Link Equalization Request bit in the Link Status 2 register was set by the hardware because it received a link equalization request from the remote node. This interrupt is enabled by the Link Equalization Interrupt Enable bit in the Link Control 3 register. The status of this interrupt can be read from the Link Equalization Request bit of the Link Status 2 register.

The pl_interrupt output is not active when the core is configured as an Endpoint.

cfg_tph_requester_enable

Output

4

Bit 0 of this output reflect the setting of the TPH Requester Enable bit [8] of the TPH Requester Control register in the TPH Requester Capability Structure of physical function 0. Bit 1 corresponds to physical function 1. Bits [3:2] are reserved.

cfg_tph_st_mode

Output

12

Bits [2:0] of this output reflect the setting of the ST Mode Select bits in the TPH Requester Control register of physical function 0. Bits [5:3] reflect the setting of the same register field of PF 1. Bits [11:6] are reserved.

cfg_vf_tph_requester_enable

Output

8

Each bit of this output reflects the setting of the TPH Requester Enable bit 8 of the TPH Requester Control register in the TPH Requester Capability Structure of the corresponding virtual function. Bits [7:6] are reserved.

cfg_vf_tph_st_mode

Output

24

Bits [2:0] of this output reflect the setting of the ST Mode Select bits in the TPH Requester Control register of virtual function 0. Bits [5:3] reflect the setting of the same register field of VF 1, and so on. Bits [23:18] are reserved.

pcie_cq_np_req

Input

1

CQ Non-Posted Request.

This input is used by the user application to request the delivery of a Non-Posted request. The core implements a credit-based flow control mechanism to control the delivery of Non-Posted requests across the interface, without blocking Posted TLPs.

This input to the core controls an internal credit count. The credit count is incremented in each clock cycle when pcie_cq_np_req is High, and decremented on the delivery of each Non-Posted request across the interface. The core temporarily stops delivering Non-Posted requests to the user application when the credit count is zero. It continues to deliver any Posted TLPs received from the link even when the delivery of Non-Posted requests has been paused.

The user application can either provide a one-cycle pulse on pcie_cq_np_req each time it is ready to receive a Non-Posted request, or can keep it High permanently if it does not need to exercise selective back pressure on Non-Posted requests.

The assertion and deassertion of the pcie_cq_np_req signal does not need to be aligned with the packet transfers on the completer request interface. There is a minimum of five user_clk from the presentation of completion on m_axis_rc_tuser and the reuse of the tag that was returned on the completion.

pcie_cq_np_req_count

Output

6

CQ Non-Posted Request Count.

This output provides the current value of the credit count maintained by the core for delivery of Non-Posted requests to the user application. The core delivers a Non-Posted request across the completer request interface only when this credit count is non-zero. This counter saturates at a maximum limit of 32.

Because of internal pipeline delays, there can be several cycles of delay between the core receiving a pulse on the pcie_cq_np_req input and updating the pcie_cq_np_req_count output in response.

This count is reset on user_reset and de-assertion of user_lnk_up.

pcie_tfc_nph_av

Output

2

This output provides an indication of the currently available header credit for Non-Posted TLPs on the transmit side of the core. The user logic can check this output before transmitting a Non-Posted request on the requester request interface, to avoid blocking the interface when no credit is available. The encodings are:

00: No credits available

01: 1 credit available

10: 2 credits available

11: 3 or more credits available

Because of pipeline delays, the value on this output can not include the credit consumed by the Non-Posted requests in the last two cycles or less. The user logic must adjust the value on this output by the credit consumed by the Non-Posted requests it sent in the previous clock cycles, if any.

pcie_tfc_npd_av

Output

2

This output provides an indication of the currently available payload credit for Non-Posted TLPs on the transmit side of the core. The user logic checks this output before transmitting a Non-Posted request on the requester request interface, to avoid blocking the interface when no credit is available. The encodings are:

00: No credits available

01: 1 credit available

10: 2 credits available

11: 3 or more credits available

Because of pipeline delays, the value on this output does not include the credit consumed by the Non-Posted requests sent by the user logic in the last two clock cycles or less. The user logic must adjust the value on this output by the credit consumed by the Non-Posted requests it sent in the previous clock cycles, if any.