This section provides guidance for migrating from the 7 series Gen2 core to the UltraScale™ devices Gen3 core.
Note: The 7 Series Gen3 core interface is the same as that of the UltraScale devices Gen3 core.
In the 7 series Gen2 core, the AXI4-Stream (and TRN) payload byte ordering matches that of the PCIe bus, because the user application is responsible for the formation of the PCIe packets. However, in the UltraScale devices Gen3 v3.1 core, the byte ordering of the payload (after the descriptor) is endian, compliant with the AXI4-Stream protocol.
This Figure in the Overview chapter shows the AXI4-Stream TX and RX interfaces.