Limitations - 4.4 English

• GTH pipe wrappers reset the QPLL when the PCIe change the rate to Gen3. The sharing core must be able to handle this situation.

• Pipe wrappers commonly use a channel phase-locked loop (CPLL) for Gen1 or Gen2 PCIe, and QPLL for Gen3. If the Gen3 PCIe can operate at a lower speed, pipe wrappers might not require a QPLL.

• The settings of the GT_COMMON should not be changed because they are optimized for the PCIe core.

Figure 3-2: Shared Logic in the Example Design

X-Ref Target - Figure 3-2