Minimum Device Requirements - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The minimum device requirements for the core are as follows:

Table 2-1: Minimum Device Requirements

Capability Link Speed

Capability Link Widths

Supported Speed Grades

Gen1

x1, x2, x4, x8

-3,-2,-1,-1L, -1LV, -1H, and -1HV

Gen2

x1, x2, x4, x8

-3,-2,-1,-1L, -1LV, -1H and -1HV

Gen3

x1, x2, x4

-3,-2,-1,-1L, -1LV, -1H and -1HV (1)

Gen3

x8

-3, -2, -1, -1H and -1HV (2) (4)

Notes:

1. The Core Clock Frequency option must be set to 250 MHz for -1LV and -1L speed grades.
The Core Clock Frequency option set to 500 MHz is supported for -3 and -2 speed grades only.

2. Gen3x8 is possible for -1, -1H and -1HV speed grades, depending on user design, but may require additional timing closure efforts. Gen3x8 is not supported for -1L and -1LV (0.9V and 0.95V) speed grade.

3. Engineering Samples (ES) may have additional restrictions. For more information, see the corresponding errata documents.

4. Speed grades -1L, -1LV are supported only for Kintex UltraScale devices.
Speed grades -1H and -1HV are supported only for Virtex UltraScale devices.