The initial configuration of the device is no different than the normal Tandem Configuration. Initial configuration of the device consists of two stages, either as a single bitstream from flash using the Tandem PROM approach, or as two separate bitstreams (one loaded using flash, one loaded over PCIe) using the Tandem PCIe approach. Both of these variations are supported in Tandem with Field Updates for UltraScale devices only, as the IP core is identical for these two approaches. After the stage 1 is loaded, only the PCIe IP is operational, with limited functionality as the rest of the design behind it does not yet exist. It is able to link train and be recognized by the Root Port in the system. After the stage 2 bitstream is loaded, the devices is in normal operational mode.
Subsequent dynamic updates follow the fundamental rules for UltraScale device partial reconfiguration . One such rule is the application of clearing files. The clearing file for the current application must be loaded before the new partial bitstream is delivered. For example, if the “ver1” version of the design is configured at power up, the ver1_partial_clear.bin must be sent to prepare the user application for ver2_partial.bin (or any new partial image version). In the next FPGA update, ver2_partial_clear.bin would be sent to prepare the region for a version 3 (ver3, or any new image, including a return to ver1).
Using the bitstream names for a Tandem PCIe design and the supplied scripts, the sequence would look like this:
1. Power on the FPGA. ver1_tpcie_tandem1.mcs is sent from local flash.
° At this point, the PCIe Endpoint is functional, and enumeration can occur.
° The PCIe core is isolated from the rest of the unconfigured device.
2. Deliver ver1_tpcie_tandem2.bin over the PCIe link.
° The complete device is now programmed, and the design switches automatically to full use mode by establishing communication between PCIe and the rest of the design.
3. Operate the FPGA for as long as you would like.
4. When a request to update is received, deliver ver1_tpcie_update_region_partial_clear.bin over the PCIe link.
° This readies the user application region; clocks to this region are disabled, so the user application is now non-functional.
° The PCIe core is isolated from the user application region as part of the software driver instructions.
5. Deliver the new user application by sending ver2_tpcie_update_region_partial.bin over the PCIe link.
° The full device is once again operational, now with new functionality.
° The switchover from isolation of the PCIe to full operation happens automatically.
6. Repeat step 4 and step 5 to move on to a new version (or return to ver1), this time starting with delivery of ver2_tpcie_update_region_partial_clear.bin . This would be followed by the next version of the user application, or a return to ver1.