Follow these steps to build the Tandem IP and compile the sample design. The Vivado Design Suite processes the design from IP customization to bitstream generation for two design configurations.
1. Launch the Customize IP dialog box to customize the UltraScale Devices Gen3 Integrated Block for PCIe core.
Note: This solution is supported only in version 4.2 (and newer) of the IP.
2. Customize the PCIe IP core with Tandem with Field Updates selected. The Advanced Mode option must be selected to see this option. If debug capabilities are desired (most designs are expected to require this), select the Use an external STARTUP primitive option.
3. Generate output products by using the default Out of context per IP synthesis option. This synthesizes the IP to create a checkpoint that can be inserted in your full design.
4. Right-click the IP in the Design Sources tab, and select Open IP Example Design .
IMPORTANT: Do not implement this sample design within the Vivado IDE in project mode.
The example design comes with a set of scripts for use with the non-project Tcl flow.The sample scripts are located in the field_update_scripts folder, but these are all referenced by the master script in the design example folder.
5. In a Vivado Tcl shell, source design_field_updates.tcl , which is found in the project directory. This file compiles the example design with two versions:
° With the default settings, Ver1 is the initial design , and is the one that is expected to be used for initial boot, so Tandem bitstreams are created.
° Ver2 is intended to be the update to Ver1, so only partial bitstreams are created.