PCIe DRP Ports - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID

PG156

Release Date

2023-11-24

Version

4.4 English

When checked, enables the PCIe DRP interface.

The signals in Table: PCIe DRP Ports are available when PCIe DRP Ports option is selected.

Table 4-5: PCIe DRP Ports
Name	Direction	Width	Description
drp_addr	I	10 bits	PCIe DRP address
drp_en	I	1 bit	PCIe DRP enable
drp_di	I	16 bits	PCIe DRP data in
drp_do	O	16 bits	PCIe DRP data out
drp_rdy	O	1 bit	PCIe DRP ready
drp_we	I	1 bit	PCIe DRP write/read
drp_clk	I	1 bit	drp_clk used for drp interface, frequencies supported are 62.5 MHz, 125 MHz and 250 MHz