The UltraScale Devices Gen3 Integrated Block for PCIe core supports the PIPE mode simulation where the PIPE interface of the core is connected to the PIPE interface of the link partner. This mode increases the simulation speed.
Use the Enable External PIPE Interface option on the Basic page of the Customize IP dialog box to enable PIPE mode simulation in the current Vivado Design Suite solution example design, in either Endpoint mode or Root Port mode. The External PIPE Interface signals are generated at the core boundary for access to the external device. Enabling this feature also provides the necessary hooks to use third-party PCI Express VIPs/BFMs instead of the Root Port model provided with the example design.
TIP: PIPE mode is for simulation only. Implementation is not supported.
For details, see Enable External PIPE Interface .
Table: Common In/Out Commands and Endpoint PIPE Signals Mappings and Table: Input/Output Buses With Endpoint PIPE Signals Mapping describe the PIPE bus signals available at the top level of the core and their corresponding mapping inside the EP core ( pcie_top ) PIPE signals.
IMPORTANT: A new file, xil_sig2pipe.v , is delivered in the simulation directory, and the file replaces phy_sig_gen.v . BFM/VIPs should interface with the xil_sig2pipe instance in board.v .
In Commands |
Endpoint PIPE Signals Mapping |
Out Commands |
Endpoint PIPE Signals Mapping |
---|---|---|---|
common_commands_in[25:0] |
not used |
common_commands_out[0] |
pipe_clk (1) |
|
|
common_commands_out[2:1] |
pipe_tx_rate_gt (2) |
|
|
common_commands_out[3] |
pipe_tx_rcvr_det_gt |
|
|
common_commands_out[6:4] |
pipe_tx_margin_gt |
|
|
common_commands_out[7] |
pipe_tx_swing_gt |
|
|
common_commands_out[8] |
pipe_tx_reset_gt |
|
|
common_commands_out[9] |
pipe_tx_deemph_gt |
|
|
common_commands_out[16:10] |
not used (3) |
Notes: 1. pipe_clk is an output clock based on the core configuration. For Gen1 rate, pipe_clk is 125 MHz. For Gen2 and Gen3, pipe_clk is 250 MHz. 2. pipe_tx_rate_gt indicates the pipe rate (2’b00-Gen1, 2’b01-Gen2 and 2’b10-Gen3). 3. This ports functionality has been deprecated and can be left unconnected. |
Input Bus |
Endpoint PIPE Signals Mapping |
Output Bus |
Endpoint PIPE Signals Mapping |
---|---|---|---|
pipe_rx_0_sigs[31:0] |
pipe_rx0_data_gt |
pipe_tx_0_sigs[31: 0] |
pipe_tx0_data_gt |
pipe_rx_0_sigs[33:32] |
pipe_rx0_char_is_k_gt |
pipe_tx_0_sigs[33:32] |
pipe_tx0_char_is_k_gt |
pipe_rx_0_sigs[34] |
pipe_rx0_elec_idle_gt |
pipe_tx_0_sigs[34] |
pipe_tx0_elec_idle_gt |
pipe_rx_0_sigs[35] |
pipe_rx0_data_valid_gt |
pipe_tx_0_sigs[35] |
pipe_tx0_data_valid_gt |
pipe_rx_0_sigs[36] |
pipe_rx0_start_block_gt |
pipe_tx_0_sigs[36] |
pipe_tx0_start_block_gt |
pipe_rx_0_sigs[38:37] |
pipe_rx0_syncheader_gt |
pipe_tx_0_sigs[38:37] |
pipe_tx0_syncheader_gt |
pipe_rx_0_sigs[83:39] |
not used |
pipe_tx_0_sigs[39] |
pipe_tx0_polarity_gt |
|
|
pipe_tx_0_sigs[41:40] |
pipe_tx0_powerdown_gt |
|
|
pipe_tx_0_sigs[69:42] |
not used (1) |
Notes: 1. This ports functionality has been deprecated and can be left unconnected. |