Configuration Interrupt Controller Interface - 4.4 English - PG156

Configuration INTx Vector

When the core is configured as EP, these four inputs are used by the user application to signal an interrupt from any of its PCI functions to the RC using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. These four inputs correspond to INTA, INTB, INTC, and INTD. Asserting one of these signals causes the core to send out an Assert_INTx message, and deasserting the signal causes the core to transmit a Deassert_INTx message.

Configuration INTx Sent

A pulse on this output indicates that the core has sent an INTx Assert or Deassert message in response to a change in the state of one of the cfg_interrupt_int inputs.

Configuration INTx Interrupt Pending (active-High)

Per function indication of a pending interrupt. cfg_interrupt_pending[0] corresponds to physical function 0 and so on. Bits [3:2] are reserved.

Configuration Interrupt MSI Function Enabled

Indicates that Message Signaling Interrupt (MSI) messaging is enabled per function. Bits [3:2] are reserved.

Configuration Interrupt MSI on VF Enabled

Indicates that MSI messaging is enabled, per virtual function. Bits [7:6] are reserved.

Configuration Interrupt MSI Vector

When the core is configured in Endpoint mode to support MSI interrupts, these inputs are used to signal the 32 distinct interrupt conditions associated with a PCI function (physical or virtual) from the user logic to the core. The function number must be specified on the cfg_interrupt_msi_function_number input. After placing the function number on the input cfg_interrupt_msi_function_number, the user logic must activate one of these signals for one cycle to transmit an interrupt. The user logic must not activate more than one of the 32 interrupt inputs in the same cycle. The core internally registers the interrupt condition on the 0-to-1 transition of any bit in cfg_interrupt_msi_int. After asserting an interrupt, the user logic must wait for the cfg_interrupt_msi_sent or cfg_interrupt_msi_fail indication from the core before asserting a new interrupt.

Configuration Interrupt MSI Interrupt Sent

The core generates a one-cycle pulse on this output to signal that an MSI interrupt message has been transmitted on the link. The user logic must wait for this pulse before signaling another interrupt condition to the core.

Configuration Interrupt MSI Interrupt Operation Failed

A one-cycle pulse on this output indicates that an MSI interrupt message was aborted before transmission on the link. The user application must retransmit the MSI interrupt in this case.

Configuration Interrupt MSI Function Multiple Message Enable

When the core is configured in the Endpoint mode to support MSI interrupts, these outputs are driven by the Multiple Message Enable bits of the MSI Control registers associated with physical functions. These bits encode the number of allocated MSI interrupt vectors for the corresponding function. Bits [2:0] correspond to physical function 0 and bits [5:4] to physical function 1. Bits [12:6] are reserved.

Configuration Interrupt MSI Pending Status

These inputs provide the status of the MSI pending interrupts for the physical functions. The setting of these pins determines the value read from the MSI Pending bits register of the corresponding PF. The MSI Pending bits register contains the pending bits for MSI Interrupts. A read from this location returns the state of MSI_MASK inputs of the core. This is a 32-bit wide RO register with a default value of MSI MASK inputs. Assert this signal together with cfg_interrupt_msi_pending_status and cfg_interrupt_msi_pending_status_function_num values to update the MSI Pending bits in the corresponding function.

Configuration Interrupt MSI Function Mask Update

Asserted for one cycle when any enabled functions in the MSI Mask register change value. MSI Mask register contains the Mask bits for MSI interrupts. The Multiple Message Capable field in the MSI Control register specifies the number of distinct interrupts for the function, which determines the number of valid mask bits. This is a 32-bit wide RW register with a default value of 0.

Configuration Interrupt MSI Select

Values 0000b-0001b correspond to PF0-1 selection, and values 0010b-0111b correspond to VF0-5 selection. cfg_interrupt_msi_data[31:0] presents the value of the MSI Mask register from the selected function. When this input is driven to 1111b, cfg_interrupt_msi_data[17:0] presents the Multiple Message Enable bits of the MSI Control registers associated with all virtual functions. These bits encode the number of allocated MSI interrupt vectors for the corresponding function. cfg_interrupt_msi_data[2:0] correspond to virtual function 0, and so on.

Configuration Interrupt MSI Data

The value presented depends on cfg_interrupt_msi_select.

cfg_interrupt_msi_pending_

status_function_num

Configuration Interrupt MSI Pending Target Function Number

You provide the function number (0-11), where values 0-3 corresponds to PF0-3, and value 4-11 corresponds to VF0-7.

cfg_interrupt_msi_pending_

status_data_enable

Configuration Interrupt MSI Pending Data Valid

Assert this signal together with cfg_interrupt_msi_pending_status and cfg_interrupt_msi_pending_status_function_num values to update the MSI Pending bits in the corresponding function.

Configuration Interrupt MSI-X Function Enabled

When asserted, indicates that the Message Signaling Interrupt (MSI-X) messaging is enabled, per function.

Configuration Interrupt MSI-X Function Mask

Indicates the state of the Function Mask bit in the MSI-X Message Control field, per function.

Configuration Interrupt MSI-X on VF Enabled

When asserted, indicates that Message Signaling Interrupt (MSI-X) messaging is enabled, per virtual function.

Configuration Interrupt MSI-X VF Mask

Indicates the state of the Function Mask bit in the MSI-X Message Control field, per virtual function.

Configuration Interrupt MSI-X Address

When the core is configured to support MSI-X interrupts, this bus is used by the user logic to communicate the address to be used for an MSI-X message.

Configuration Interrupt MSI-X Data

When the core is configured to support MSI-X interrupts, this bus is used by the user logic to communicate the data to be used for an MSI-X message.

Configuration Interrupt MSI-X Data Valid

This signal indicates that valid information has been placed on the cfg_interrupt_msix_address[63:0] and cfg_interrupt_msix_data[31:0] buses, and the originating function number has been placed on cfg_interrupt_msi_function_number[3:0]. The core internally registers the associated address and data from cfg_interrupt_msix_address and cfg_interrupt_msix_data on the 0-to-1 transition of this valid signal. The user application must ensure that the cfg_interrupt_msix_enable bit corresponding to function in use is set before asserting cfg_interrupt_msix_int. After asserting an interrupt, the user logic must wait for the cfg_interrupt_msix_sent or cfg_interrupt_msix_fail indication from the core before asserting a new interrupt.

Configuration Interrupt MSI-X Interrupt Sent

The core generates a one-cycle pulse on this output to indicate that it has accepted the information placed on the cfg_interrupt_msix_address[63:0] and cfg_interrupt_msix_data[31:0] buses, and an MSI-X interrupt message has been transmitted on the link. The user application must wait for this pulse before signaling another interrupt condition to the core.

Configuration Interrupt MSI-X Interrupt Operation Failed

A one-cycle pulse on this output indicates that the interrupt controller has failed to transmit MSI-X interrupt on the link. The user application must retransmit the MSI-X interrupt in this case.

Configuration Interrupt MSI/MSI-X TLP Attr

These bits provide the setting of the Attribute bits to be used for the MSI/MSI-X interrupt request. Bit 0 is the No Snoop bit, and bit 1 is the Relaxed Ordering bit. Bit 2 is the ID-Based Ordering bit. The core samples these bits on a 0-to-1 transition on cfg_interrupt_msi_int or cfg_interrupt_msix_int.

Configuration Interrupt MSI/MSI-X TPH Present

Indicates the presence of a Transaction Processing Hint (TPH) in the MSI/MSI-X interrupt request. The user application must set this bit while asserting cfg_interrupt_msi_int or cfg_interrupt_msix_int, if it includes a TPH in the MSI or MSI-X transaction.

Configuration Interrupt MSI/MSI-X TPH Type

When cfg_interrupt_msi_tph_present is 1'b1, these two bits supply the two-bit type associated with the hint. The core samples these bits on a 0-to-1 transition on cfg_interrupt_msi_int or cfg_interrupt_msix_int.

Configuration Interrupt MSI/MSI-X TPH Steering Tag

When cfg_interrupt_msi_tph_present is 1'b1, the Steering Tag associated with the Hint must be placed on cfg_interrupt_msi_tph_st_tag[7:0]. Setting cfg_interrupt_msi_tph_st_tag[8] to 1b activates the Indirect Tag mode. In the Indirect Tag mode, the core uses bits [5:0] of cfg_interrupt_msi_tph_st_tag as an index into its Steering Tag Table (STT) in the TPH Capability Structure (STT is limited to 64 entries per function), and inserts the tag from this location in the transmitted request MSI/X TLP. Setting cfg_interrupt_msi_tph_st_tag[8] to 0b activates the Direct Tag mode. In the Direct Tag mode, the core inserts cfg_interrupt_msi_tph_st_tag[7:0] directly as the Tag in the transmitted MSI/X TLP. The core samples these bits on a 0-to-1 transition on any cfg_interrupt_msi_int bits or cfg_interrupt_msix_int.

Configuration MSI/MSI-X Initiating Function

Indicates the Endpoint function number initiating the MSI or MSI-X transaction:

• 0: PF0
• 1: PF1
• 2: Not used
• 3: Not used
• 4: VF0
• 5: VF1
• 6: VF2
• 7: VF3
• 8: VF4
• 9: VF5