Shared GT_COMMON - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

A quad phase-locked loop (QPLL) in GT_COMMON can serve a quad of GT_CHANNEL instances. If the PCIe core is configured as X1 or X2 and is using a QPLL, the remaining GT_CHANNEL instances can be used by other cores by sharing the same QPLL and GT_COMMON.

To use the shared GT_COMMON instances, select the Include Shared Logic in example design option on the Shared Logic tab. When this feature is selected, the GT_COMMON instance is moved from the pipe wrappers to the support wrapper of the example design. It also enables additional ports to the top level to facilitate sharing of GT_COMMON.

Shared logic for GT_COMMON helps conserve FPGA resources and also reduces dedicated clock routing within the single GT quad.