AXI-ST Interface Width - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The core allows you to select the Interface Width, as defined in Table: Lane Width, Link Speed, and Interface Width . The default interface width set in the Customize IP dialog box is the lowest possible interface width.

Table 4-3: Lane Width, Link Speed, and Interface Width

Lane Width

Link Speed (Gb/s)

Interface Width (Bits)

x8

8.0

256