AXI-ST Interface Width - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The core allows you to select the Interface Width, as defined in the following table. The default interface width set in the Customize IP dialog box is the lowest possible interface width.

Table 1. Lane Width, Link Speed, and Interface Width
Lane Width Link Speed (Gb/s) Interface Width (Bits)
x8 8.0 256