This feature allows you to share common logic across multiple instances of PCIe® blocks or with other cores, with certain limitations. Shared logic minimizes the HDL modifications needed by locating the logic to be shared to the top module of the design. It also enables additional ports on the top module to facilitate sharing. Shared logic is applicable for both Endpoint mode and Root Port mode.
In the AMD Vivado™ Design Suite, the shared logic options are available in the Shared Logic page when customizing the core.
There are two types of logic sharing:
- Shared logic in the core
- Shared logic in the example design
In both cases, the GT_COMMON block is shared.
- In the case of Gen1 speeds, the design uses CPLL, hence it cannot be shared and the shared logic feature is disabled.
- In the case of Gen2 speeds, QPLL1 or CPLL can be selected. If CPLL is selected (using the PLL Selection option on GT Settings Page) the Shared Logic page is disabled.