Post-Synthesis/Post-Implementation Netlist Simulation - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The UltraScale Devices Gen3 Integrated Block for PCIe core supports post-synthesis/post-implementation netlist functional simulations. However, some configurations do not support this feature in this release. See Table: Configuration Support for Functional Simulation for the configuration support of netlist functional simulations.

Note: Post-synthesis/implementation netlist timing simulations are not supported for any of the configurations this release.

Table 4-13: Configuration Support for Functional Simulation

Configuration

Verilog

VHDL

External PIPE
Interface Mode

Shared Logic in Core

Shared Logic in Example Design

Endpoint

Yes

Yes (Except Tandem mode with External Startup Primitive selected)

No

Yes

Yes

Root Port

Not Supported at this time