The UltraScale Devices Gen3 Integrated Block for PCIe core supports post-synthesis/post-implementation netlist functional simulations. However, some configurations do not support this feature in this release. See the following table for the configuration support of netlist functional simulations.
Note: Post-synthesis/implementation netlist timing simulations are not
supported for any of the configurations this release.
| Configuration | Verilog | VHDL | External PIPE Interface Mode | Shared Logic in Core | Shared Logic in Example Design |
|---|---|---|---|---|---|
| Endpoint | Yes | Yes (Except Tandem mode with External Startup Primitive selected) | No | Yes | Yes |
| Root Port | Not Supported at this time | ||||