Revision History - 4.4 English

11/24/2023

4.4

• Updated PCIe DRP Ports table.

• Updated Enable In System IBERT section.

12/12/2022

4.4

• Added Dynamic Function eXchange feature related information.

• Updated Figures 3-4, 3-6, 3-7, 3-9, 3-10, and 3-11.

11/25/2022

4.4

• Updated GT Settings Tab figure.

• Added GT DRP Clock Source section.

• Added Disable GT Channel LOC Constraints section.

04/04/2018

4.4

• All new “GT Locations” appendix.

• Added Integrated Debug Options to “Debugging” appendix.

12/20/2017

4.4

• Removed documented support for Resizable BAR (RBAR).

In Chapter 2, “Product Specification”:

• Added details about phy_rdy_output signal in Clock and Reset Interface section.

In Chapter 3, “Designing with the Core”:

• Added note regarding configuration bank 65 in the Tandem Configuration section.

• Updated the Legacy Interrupt Signaling figure and description.

10/04/2017

4.4

In Chapter 1, “Overview”:

• Updated Table 2-1: Available Integrated Block for PCI Express.

In Chapter 2, “Product Specification”:

• Updated the documented cfg_mgmt_addr width.

• Minor updates to description for cfg_current_speed, cfg_max_payload, cfg_max_read_req, cfg_err_cor_out, cfg_err_nonfatal_out, cfg_err_fatal_out, cfg_local_error.

• Major updates to description for cfg_interrupt_msi_function_number, cfg_ext_read_data_valid.

In Chapter 3, “Designing with the Core”:

• Updated the Tandem Configuration section.

• Major updates to description for Completer Completion Descriptor Fields Bit Indexes 79:72, 87:80, and 88.

• Major updates to description for Requester Request Descriptor Fields Bit Indexes 87:80, 95:88, and 120.

In Chapter 4, “Design Flow Steps”:

• Added further details to the following Vivado IP catalog option:

° PF0 ID Initial Values > Device ID value (in Identity Setting (PF0 IDs and PF1 IDs) tab).

° MSIx Table Settings > Table Size (in MSI-X Capabilities tab).

In Appendix A, “Upgrading”:

• Updated Port and Parameters changes for the current core version.

New Appendix D, “Using Xilinx Virtual Cable to Debug.”

06/07/2017

4.3

• Minor updates to the Tandem Configuration section.

• Updated port description for cfg_interrupt_msi_pending_status.

• Updated MSI Mode figure.

04/05/2017

4.3

In Chapter 3, “Designing with the Core”:

• Added the GT Wizard option to the Shared Logic section.

• Updated the Tandem Configuration section.

In Chapter 4, “Design Flow Steps”:

• Added PCIe DRP Ports and GT DRP Ports tables.

• Added support for Gen1 and Gen2 speed links to the Enable In System IBERT option.

12/19/2016

4.2

• In Chapter 4, “Design Flow Steps”, clarified that the Enable In System IBERT option should be used only for hardware debugging. Simulations are not supported for the cores generated using these options.

11/30/2016

4.2

Vivado IP catalog core option changes:

• Added ECRC check capable sub option to the Enable AER Capability option in the Extended Capabilities 1 and Extended Capabilities 2 tab .

• Clarified the effect of Enable Auto RxEq setting on the LPM or DFE setting in the GT Settings tab.

10/19/2016

4.2

• Editorial updates in Chapter 2, “Product Specification”.

10/05/2016

4.2

• Moved the performance and resource utilization data to the web.

• Updated the Tandem Configuration section.

• Updated the BAR Size Ranges for Device Configuration table in the Design Flow Steps chapter.

• Added the Enable Parity option to the Basic tab (Advanced Mode), the Enable Auto RxEq option to the GT Settings tab, and added the Enable In System IBERT, Enable Descrambler for Gen3 Mode, and Enable JTAG Debugger parameters in the new Add. Debug Options tab in the Design Flow Steps chapter.

• Updated the Parameter Changes table and Ports Changes table in the Migrating and Updating appendix.

06/08/2016

4.2

• Updated Tandem Configuration section

• Updated Generating Interrupt Requests

• New device GT locations added.

04/06/2016

4.2

• In the Tandem Configuration section:

° Updated the Tandem PROM/PCIe Support Configurations table.

° Added the Tandem with Field Updates section.

° Added the Debugging Tandem with Field Updates Designs section.

• Added new Parameters Changes and Ports Changes table to the Migrating and Updating appendix.

• Updated the Kintex UltraScale Device GT Locations table.

01/29/2016

4.1

• Updated Table: 2-2 Available Integrated Blocks for PCI Express.

11/20/2015

4.1

• Updated details for Gen3 in Table 2-3: Minimum Device Requirements.

11/18/2015

4.1

• Added the FFVA1156 package to the XCKU095 device in the Available Integrated Blocks For PCI Express table (Chapter 2), and Kintex ™ UltraScale™ Device GT Locations table (Appendix B).

• Updated the supported speed grades.

• Updated the width for the following ports: cfg_function_status, cfg_vf_status, cfg_function_power_state, cfg_vf_power_state, cfg_rcb_status, cfg_dpa_substate_change, cfg_tph_requester_enable, cfg_tph_st_mode, cfg_vf_tph_requester_enable, cfg_vf_tph_st_mode, cfg_vf_flr_in_process, cfg_per_function_number, cfg_flr_done, cfg_flr_in_process, cfg_interrupt_pending, cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable, and cfg_interrupt_msi_mmenable.

• Added available negotiated link width values for cfg_negotiated_width.

• Updated the status (Not Supported, Beta, Production) in the Tandem PROM/PCIe Supported Configurations table.

• Removed the Message Signal Interrupt option from the Vivado IDE.

• Added the Enable RX Message INTFC option to the Vivado IDE.

09/30/2015

4.1

• Updated the available integrated blocks for PCIe.

• Updated the Tandem Configuration section.

• Updated PIPE signal mapping tables: Common In/Out Commands and Endpoint PIPE Signals Mappings, and Input/Output Bus with Endpoint PIPE Signals Mapping.

• Updated the recommended Virtex ™ UltraScale device, and Kintex UltraScale device GT locations.

07/02/2015

4.0

• Corrected resource utilization data.

06/24/2015

4.0

• Updated the available integrated blocks for PCI Express.

• Added the Minimum Device Requirements table.

• Updated the documented m_axis_cq_tdata signal width.

• Updated the signal description for addr_offset[2:0].

• Added the sys_clk_gt signal.

• Updated the Common PCI Configuration Space Header table.

• Updated the USER_CLK2_FREQ attribute values.

• Added an Important note regarding when Shared Logic is available.

• Updated the Tandem Configuration section.

• Added the Receive Ordering Rules table (Receive Transaction Ordering section).

• Added the Relocating the Integrated Block Core section.

• GT locations:

° Renamed core pinouts to GT locations throughout.

° Added command to print specific package pins for a GT location.

° Updated the Recommended Virtex UltraScale GT Locations table.

05/07/2015

4.0

• Updated the Tandem Configuration section.

04/01/2015

4.0

• Updated Clock and Reset Interface port descriptions: sys_reset, pcie_perstn0_out, pcie_perstn1_in, and pcie_perstn1_out.

• Updated the core pinouts information.

• Updated the tandem configuration information.

• Added core parameters: Additional Transceiver Control and Status Ports, CORE CLOCK Frequency, PLL Selection, and Link Partner TX Preset.

• Updated parameters: Legacy Interrupt Settings, and MSI Capabilities.

• Moved existing parameters to new GT Settings tab: PPM Offset between receiver and transmitter, Spread spectrum clocking, and Insertion loss at Nyquist.

• Added support for post-synthesis and post-implementation netlist simulation for Endpoint configuration.

• Added support for Pipe Mode implementation.

• Added configurator design example details.

02/23/2015

3.1

• Updated the device selection and PCIe integrated block location information.

• Updated the device core pinouts.

• Clarified information regarding Pipe Mode Simulation.

• Corrected the minimum 32-bit BARs number and the maximum 64-bit BARs number for the Base Address Register Overview parameter (per the
Vivado IDE).

11/19/2014

3.1

• Updated the Configuration Space section with Media Configuration Access Port (MCAP) Extended Capability Structure.

• Updated the tandem configuration information.

• Added support for Cadence Incisive Enterprise Simulator (IES) and Synopsys Verilog Compiler Simulator (VCS).

• Updated the device core pinouts.

10/01/2014

3.1

• Updated for core v3.1.

• Updated the tandem configuration information.

• Added package migration information for UltraScale device designs.

06/04/2014

3.0

• Updated device information.

04/02/2014

3.0

• Updated block selection.

• Updated core pinout information.

• Updated shared logic information.

12/18/2013

2.0

Initial release.