|
Port
|
Direction
|
Width
|
Description
|
|
gt_pcieuserratedone
|
I
|
1
|
Connects to PCIEUSERRATEDONE on transceiver channel primitives
|
|
gt_loopback
|
I
|
3
|
Connects to LOOPBACK on transceiver channel primitives
|
|
gt_txprbsforceerr
|
I
|
1
|
Connects to TXPRBSFORCEERR on transceiver channel primitives
|
|
gt_txinhibit
|
I
|
1
|
Connects to TXINHIBIT on transceiver channel primitives
|
|
gt_txprbssel
|
I
|
4
|
PRBS input
|
|
gt_rxprbssel
|
I
|
4
|
PRBS input
|
|
gt_rxprbscntreset
|
I
|
1
|
Connects to RXPRBSCNTRESET on transceiver channel primitives
|
|
gt_txelecidle
|
O
|
1
|
Connects to TXELECIDLE on transceiver channel primitives
|
|
gt_txresetdone
|
O
|
1
|
Connects to TXRESETDONE on transceiver channel primitives
|
|
gt_rxresetdone
|
O
|
1
|
Connects to RXRECCLKOUT on transceiver channel primitives
|
|
gt_rxpmaresetdone
|
O
|
1
|
Connects to TXPMARESETDONE on transceiver channel primitives
|
|
gt_txphaligndone
|
O
|
1
|
Connects to TXPHALIGNDONE of transceiver channel primitives
|
|
gt_txphinitdone
|
O
|
1
|
Connects to TXPHINITDONE of transceiver channel primitives
|
|
gt_txdlysresetdone
|
O
|
1
|
Connects to TXDLYSRESETDONE of transceiver channel primitives
|
|
gt_rxphaligndone
|
O
|
1
|
Connects to RXPHALIGNDONE of transceiver channel primitives
|
|
gt_rxdlysresetdone
|
O
|
1
|
Connects to RXDLYSRESETDONE of transceiver channel primitives
|
|
gt_rxsyncdone
|
O
|
1
|
Connects to RXSYNCDONE of transceiver channel primitives
|
|
gt_eyescandataerror
|
O
|
1
|
Connects to EYESCANDATAERROR on transceiver channel primitives
|
|
gt_rxprbserr
|
O
|
1
|
Connects to RXPRBSERR on transceiver channel primitives
|
|
gt_dmonitorout
|
O
|
16
|
Connects to DMONITOROUT on transceiver channel primitives
|
|
gt_rxcommadet
|
O
|
1
|
Connects to RXCOMMADETEN on transceiver channel primitives
|
|
gt_phystatus
|
O
|
1
|
Connects to PHYSTATUS on transceiver channel primitives
|
|
gt_rxvalid
|
O
|
1
|
Connects to RXVALID on transceiver channel primitives
|
|
gt_rxcdrlock
|
O
|
1
|
Connects to RXCDRLOCK on transceiver channel primitives
|
|
gt_pcierateidle
|
O
|
1
|
Connects to PCIERATEIDLE on transceiver channel primitives
|
|
gt_pcieuserratestart
|
O
|
1
|
Connects to PCIEUSERRATESTART on transceiver channel primitives
|
|
gt_gtpowergood
|
O
|
1
|
Connects to GTPOWERGOOD on transceiver channel primitives
|
|
gt_cplllock
|
O
|
1
|
Connects to CPLLLOCK on transceiver channel primitives
|
|
gt_rxoutclk
|
O
|
1
|
Connects to RXOUTCLK on transceiver channel primitives
|
|
gt_rxrecclkout
|
O
|
1
|
Connects to RXRECCLKOUT on transceiver channel primitives
|
|
gt_qpll1lock
|
O
|
1
|
Connects to QPLL1LOCK on transceiver common primitives
|
|
gt_rxstatus
|
O
|
3
|
Connects to RXSTATUS on transceiver channel primitives
|
|
gt_rxbufstatus
|
O
|
3
|
Connects to RXBUFSTATUS on transceiver channel primitives
|
|
gt_bufgtdiv
|
O
|
9
|
Connects to BUFGTDIV on transceiver channel primitives
|
|
phy_txeq_ctrl
|
O
|
2
|
PHY TX Equalization control bits
|
|
phy_txeq_preset
|
O
|
4
|
PHY TX Equalization Preset bits
|
|
phy_rst_fsm
|
O
|
4
|
PHY RST FSM state bits
|
|
phy_txeq_fsm
|
O
|
3
|
PHY RX Equalization FSM state bits (Gen3)
|
|
phy_rxeq_fsm
|
O
|
3
|
PHY TX Equalization FSM state bits (Gen3)
|
|
phy_rst_idle
|
O
|
1
|
PHY is in IDLE state
|
|
phy_rrst_n
|
O
|
1
|
Synchronized reset generation by sys_clk
|
|
phy_prst_n
|
O
|
1
|
Synchronized reset generation by pipe_clk
|