PF0 SRIOV BARs and PF1 SRIVO BARs Tab - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The SRIOV Base Address Registers (BARs) set the base address register space for the Endpoint configuration. Each BAR (0 through 5) configures the SRIOV BAR Aperture Size and SRIOV Control attributes.

Table 4-7: Example Virtual Function Mappings

Physical Function

Virtual Function

Function Number Range

PF0

VF0

64

PF0

VF1

65

PF1

VF0

66

PF1

VF1

67

PF1

VF1

68