The PCI Express Root Port Model is a robust test bench environment that provides a test program interface that can be used with the provided Programmed Input/Output (PIO) design or with your design. The purpose of the Root Port Model is to provide a source mechanism for generating downstream PCI Express TLP traffic to stimulate the customer design, and a destination mechanism for receiving upstream PCI Express TLP traffic from the customer design in a simulation environment.
Source code for the Root Port Model is included to provide the model for a starting point for your test bench. All the significant work for initializing the core configuration space, creating TLP transactions, generating TLP logs, and providing an interface for creating and verifying tests are complete, allowing you to dedicate efforts to verifying the correct functionality of the design rather than spending time developing an Endpoint core test bench infrastructure.
The Root Port Model consists of:
• Test Programming Interface (TPI), which allows you to stimulate the Endpoint device for the PCI Express
• Example tests that illustrate how to use the test program TPI
• Verilog source code for all Root Port Model components, which allow you to customize the test bench
This Figure illustrates the illustrates the Root Port Model coupled with the PIO design.
