Certain input ports to the core are multiplexed so that
they are disabled during the stage 2 configuration process. These MUXes are controlled by the
mcap_design_switch signal.
These inputs are held in a deasserted state while the stage
2 bitstream is loaded. This masks off any unwanted glitches due to the absence of stage 2
logic and keeps the PCIe core in a valid state. When
mcap_design_switch is asserted, the MUXes are switched, and all interface
signals behave as described in this document.