Ce r t ai n in p u t po r t s t o th e co r e a r e m u ltiple x e d s o tha t th e y a r e d i sable d d urin g th e stage 2 configuration p r ocess . These MUXes are controlled by the mcap_design_switch signal.
These inputs are held in a deasserted state while the stage 2 bitstream is loaded. This masks off any unwanted glitches due to the absence of stage 2 logic and keeps the PCIe core in a valid state. W he n mcap_design_switch i s asse r t ed , th e MUXe s a r e swi t c h ed , an d al l interface signals b e hav e a s describ e d i n thi s docum e nt.