Design Flow Steps - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

This chapter describes customizing and generating the core, constraining the core, and the simulation, synthesis and implementation steps that are specific to this IP core. More detailed information about the standard Vivado design flows and the IP integrator can be found in the following Vivado Design Suite user guides:

Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 15]

Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 14]

Vivado Design Suite User Guide: Getting Started (UG910) [Ref 16]

Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 18]