m_axis_rx_tstrb (64-Bit Interface Only) - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The following table shows the Requester Completion interface signals used to generate the m_axis_rx_tstrb signal bus.

Table 1. RC Interface Signals for m_axis_rx_tstrb
AXI4-Stream (Enhanced)RC Interface Name Mnemonic
m_axis_rc_tkeep (Data Width/32)  
m_axis_rc_tuser[31:0] byte_en [31:0]