The ports in
Table: GT Wizard in Core Ports
appear when Shared Logic option
GT Wizard in Core
is selected.
Table A-2:
GT Wizard in Core Ports
|
Name
|
Direction
|
Width (depends on link width selected)
|
|
rxdfeagchold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfecfokhold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfelfhold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfekhhold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap2hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap3hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap4hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap5hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap6hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap7hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap8hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap9hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap10hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap11hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap12hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap13hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap14hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfetap15hold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfeuthold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxdfevphold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxoshold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxlpmgchold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxlpmhfhold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxlpmlfhold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
|
rxlpmoshold_in
|
Out
|
PL_LINK_CAP_MAX_LINK_WIDTH
|
The ports in
Table: MSI-X Ports
appear at the core boundary when the MSI-X is enabled.
Table A-3:
MSI-X Ports
|
Name
|
Direction
|
Width (depends on link width selected)
|
|
cfg_interrupt_msi_function_number
|
In
|
4 Bits
|