Tandem PROM and Tandem PCIe solutions are only supported in the Vivado Design Suite. The tool flow for both solutions is as follows:
1. Customize the core: select a supported device from Table: Tandem PROM/PCIe Supported Configurations , select the Advanced configuration Mode option, and select Tandem for the Tandem Configuration or Dynamic Function eXchange option.
2. Generate the core.
3. Open the example project, and implement the example design.
4. Use the IP and XDC from the example project in your project, and instantiate the core.
5. Synthesize and implement your design.
6. Generate bit and then prom file s.
As part of the Tandem flows, certain elements located outside of the PCIe core logic must also be brought up as part of the stage 1 bitstream. Vivado design rule checks (DRCs) identify these situations and provide direction on how to resolve the issue. This normally consists of modifying or adding additional constraints to the design.
When the example design is created, an example XDC file is generated with certain constraints that need to be copied over into your XDC file for your specific project. The specific constraints are documented in the example design XDC file. In addition, this example design XDC file contains examples of how to set options for flash memory devices, such as BPI and SPI.
When generating the PCIe IP, you will see there is no distinction between Tandem PROM and Tandem PCIe. Both methodologies generate the same IP core, so the selection in the Vivado IDE is simply Tandem . The divergence point is at the write_bitstream step, where a property (HD.TANDEM_BITSTREAMS) defines whether one BIT file (Tandem PROM) or two BIT files (Tandem PCIe) are needed. The core and corresponding implementation results are identical.