Configuration Extend Interface - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

The Configuration Extend interface allows the core to transfer configuration information with the user application when externally implemented configuration registers are implemented. Table: Configuration Extend Interface Port Descriptions defines the ports in the Configuration Extend interface of the core.

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Table 2-20: Configuration Extend Interface Port Descriptions

Port

Direction

Width

Description

cfg_ext_read_received

Output

1

Configuration Extend Read Received

The core asserts this output when it has received a configuration read request from the link. When neither user-implemented legacy or extended configuration space is enabled, receipt of a configuration read results in a one-cycle assertion of this signal, together with valid cfg_ext_register_number and cfg_ext_function_number. When user-implemented legacy, extended configuration space, or both are enabled, for the cfg_ext_register_number ranges, 0x10-0x1f or 0x120-0x3ff , respectively, this signal is asserted, until user logic presents cfg_ext_read_data and cfg_ext_read_data_valid. For cfg_ext_register_number ranges outside 0x10 - 0x1f or 0x120 - 0x3ff , receipt of a configuration read always results in a one-cycle assertion of this signal.

cfg_ext_write_received

Output

1

Configuration Extend Write Received

The core generates a one-cycle pulse on this output when it has received a configuration write request from the link.

cfg_ext_register_number

Output

10

Configuration Extend Register Number

The 10-bit address of the configuration register being read or written. The data is valid when cfg_ext_read_received or cfg_ext_write_received is High.

cfg_ext_function_number

Output

8

Configuration Extend Function Number

The 8-bit function number corresponding to the configuration read or write request. The data is valid when cfg_ext_read_received or cfg_ext_write_received is High.

cfg_ext_write_data

Output

32

Configuration Extend Write Data

Data being written into a configuration register. This output is valid when cfg_ext_write_received is High.

cfg_ext_write_byte_enable

Output

4

Configuration Extend Write Byte Enable

Byte enables for a configuration write transaction.

cfg_ext_read_data

Input

32

Configuration Extend Read Data

You can provide data from an externally implemented configuration register to the core through this bus. The core samples this data on the next positive edge of the clock after it sets cfg_ext_read_received High, if you have set cfg_ext_read_data_valid.

cfg_ext_read_data_valid

Input

1

Configuration Extend Read Data Valid

The user application asserts this input to the core to supply data from an externally implemented configuration register. The core samples this input data on the next positive edge of the clock after it sets cfg_ext_read_received High.

Note: The core will time-out the read request after 40000h (2 18 ) clock cycles of user_clk if cfg_ext_read_received signal is not asserted.