In general, to achieve the best (smallest) first-stage bitstream size, you should use the dedicated reset routing and dedicated PCIe reset package pin (PERSTN0). This selection is enabled by default where applicable. If your system design does not allow for the use of this dedicated reset, you must disable the use of the dedicated PERST routing resources in the Vivado IDE. When selecting a new location for the reset pin, you should consider the location for any I/Os that are intended to be configured in stage 1. I/Os that are physically placed a long distance from the core cause extra configuration frames to be included in the first stage. This is due to extra routing resources that are required to include these I/Os in the first stage.
Regardless of where the reset pin is located, bank 65 should still be kept in stage 1. Even if configuration modes such as QSPI are used, the EMCCLK is required for the fastest possible configuration, and that dual-mode pin is located in bank 65.