The PCI configuration space consists of three primary parts, illustrated in Table: Common PCI Configuration Space Header . These include:
• Legacy PCI v3.0 Type 0/1 Configuration Space Header
° Type 0 Configuration Space Header used by Endpoint applications (see Table: Type 0 PCI Configuration Space Header )
° Type 1 Configuration Space Header used by Root Port applications (see Table: Type 1 PCI Configuration Space Header )
• Legacy Extended Capability Items
° PCIe Capability Item
° Power Management Capability Item
° Message Signaled Interrupt (MSI) Capability Item
° MSI-X Capability Item (optional)
• PCIe Capabilities
° Advanced Error Reporting Extended Capability Structure (AER)
° Alternate Requester ID (ARI) (optional)
° Device Serial Number Extended Capability Structure (DSN) (optional)
° Power Budgeting Enhanced
° Capability Header (PB) (optional)
° Latency Tolerance Reporting (LTR) (optional)
° Dynamic Power Allocation (DPA) (optional)
° Single Root I/O Virtualization (SR-IOV) (optional)
° Transaction Processing Hints (TPH) (optional)
° Virtual Channel Extended Capability Structure (VC) (optional)
• PCIe Extended Capabilities
° Device Serial Number Extended Capability Structure (optional)
° Virtual Channel Extended Capability Structure (optional)
° Advanced Error Reporting Extended Capability Structure (optional)
° Media Configuration Access Port (MCAP) Extended Capability Structure (optional)
The core implements up to four legacy extended capability items.
For more information about enabling this feature, see Chapter 4, Customizing and Generating the Core .
The core can implement up to ten PCI Express Extended Capabilities. The remaining PCI Express Extended Capability Space is available for users to implement. The starting address of the space available to users begins at 480h . If you choose to implement registers in this space, you can select the starting location of this space, and this space must be implemented in the user application.
For more information about enabling this feature, see Extended Capabilities 1 and Extended Capabilities 2 in Chapter 4 .
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31 |
16 |
15 |
0 |
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|---|---|---|---|---|---|
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Device ID |
Vendor ID |
000h |
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Status |
Command |
004h |
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Class Code |
Rev ID |
008h |
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BIST |
Header |
Lat Timer |
Cache Ln |
00Ch |
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Header Type Specific (see Table: Type 0 PCI Configuration Space Header and Table: Type 1 PCI Configuration Space Header ) |
010h |
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014h |
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018h |
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01Ch |
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020h |
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024h |
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028h |
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02Ch |
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030h |
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CapPtr |
034h |
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038h |
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Intr Pin |
Intr Line |
03Ch |
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Reserved |
040h-
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PM Capability |
NxtCap |
PM Cap |
080h |
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Data |
Reserved |
PMCSR |
084h |
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Reserved |
088h-
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Customizable (1) |
MSI Control |
NxtCap |
MSI Cap |
090h |
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Message Address (Lower) |
094h |
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Message Address (Upper) |
098h |
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Reserved |
Message Data |
09Ch |
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Mask Bits |
0A0h |
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Pending Bits |
0A4h |
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Reserved |
0A8h-
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Optional (3) |
MSl-X Control |
NxtCap |
MSl-X Cap |
0B0h |
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Table Offset |
Table BIR |
0B4h |
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PBA Offset |
PBA BIR |
0B8h |
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Reserved |
0BCh |
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PE Capability |
NxtCap |
PE Cap |
0C0h |
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PCI Express Device Capabilities |
0C4h |
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Device Status |
Device Control |
0C8h |
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PCI Express Link Capabilities |
0CCh |
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Link Status |
Link Control |
0D0h |
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Root Port Only (2) |
Slot Capabilities |
0D4h |
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Slot Status |
Slot Control |
0D8h |
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Root Capabilities |
Root Control |
0DCh |
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Root Status |
0E0h |
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PCI Express Device Capabilities 2 |
0E4h |
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Device Status 2 |
Device Control 2 |
0E8h |
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PCI Express Link Capabilities 2 |
0ECh |
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Link Status 2 |
Link Control 2 |
0F0h |
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Unimplemented Configuration Space
|
0F4h-
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Always Enabled |
Next Cap |
Cap. Ver. |
PCI Express Extended Cap. ID (AER) |
100h |
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Uncorrectable Error Status Register |
104h |
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Uncorrectable Error Mask Register |
108h |
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Uncorrectable Error Severity Register |
10Ch |
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Correctable Error Status Register |
110h |
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Correctable Error Mask Register |
114h |
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Advanced Error Cap. and Control Register |
118h |
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Header Log Register 1 |
11Ch |
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Header Log Register 2 |
120h |
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Header Log Register 3 |
124h |
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Header Log Register 4 |
128h |
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Reserved |
12Ch |
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Optional, Root Port only (3) |
Root Error Command Register |
130h |
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Root Error Status Register |
134h |
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Error Source ID Register |
138h |
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Reserved |
13Ch |
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Next Cap |
Cap. Ver. |
PCI Express Extended Capability - Alternate Requester ID (ARI) |
140h |
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Control |
Next Function |
Function Groups |
144h |
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Reserved |
148h-
|
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Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability - DSN |
150h |
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PCI Express Device Serial Number (1st) |
154h |
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PCI Express Device Serial Number (2nd) |
158h |
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Reserved |
15Ch |
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Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability - Power Budgeting Enhanced Capability Header |
160h |
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Reserved |
DS |
164h |
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Reserved |
Power Budget Data - State D0, D1, D3, ... |
168h |
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Power Budget Capability |
16Ch |
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Reserved |
170h-
|
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Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability ID - Latency Tolerance Reporting (LTR) |
1B8h |
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No-Snoop |
Snoop |
1BCh |
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Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability ID - Dynamic Power Allocation |
1C0h |
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Capability Register |
1C4h |
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Latency Indicator |
1C8h |
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Control |
Status |
1CCh |
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Power Allocation Array Register 0 |
1D0h |
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Power Allocation Array Register 1 |
1D4h |
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Reserved |
1D8h-
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Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability ID - Single Root I/O Virtualization (SR-IOV) |
200h |
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Capability Register |
204h |
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SR-IOV Status (not supported) |
Control |
208h |
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Total VFs |
Initial VFs |
20Ch |
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Function Dependency Link |
Number VFs |
210h |
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VF Stride |
First VF Offset |
214h |
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VF Device ID |
Reserved |
218h |
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Supported Page Sizes |
21Ch |
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System Page Size |
220h |
||||
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VF Base Address Register 0 |
224h |
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VF Base Address Register 1 |
228h |
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VF Base Address Register 2 |
22Ch |
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VF Base Address Register 3 |
230h |
||||
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VF Base Address Register 4 |
234h |
||||
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VF Base Address Register 5 |
238h |
||||
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Reserved |
23Ch |
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|
Reserved |
240h-
|
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Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability ID - Transaction Processing Hints (TPH) |
274h |
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|
Capability Register |
278h |
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Requester Control Register |
27Ch |
||||
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Reserved |
Steering Tag Upper |
Steering Tag Lower |
280h |
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|
|
Reserved |
284h - 2FCh |
|||
|
Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability ID - Secondary PCIe Extended Capability |
300h |
|
|
Lane Control (not supported) |
304h |
||||
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Reserved |
Lane Error Status |
308h |
|||
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Lane Equalization Control Register 0 |
30Ch |
||||
|
Lane Equalization Control Register 1 |
310h |
||||
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Lane Equalization Control Register 2 |
314h |
||||
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Lane Equalization Control Register 3 |
318h |
||||
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|
Reserved |
31Ch-
|
|||
|
Next Cap |
Cap. Ver. |
PCI Express Extended Capability ID - MCAP |
340h |
||
|
Capability Register |
344h |
||||
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FPGA JTAG ID |
348h |
||||
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FPGA Bitstream Version |
34Ch |
||||
|
Status Register |
350h |
||||
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Control Register |
354h |
||||
|
Data Write Register |
358h |
||||
|
Read Data 0 Register |
35Ch |
||||
|
Read Data 1 Register |
360h |
||||
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Read Data 2 Register |
364h |
||||
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Read Data 3 Register |
368h |
||||
|
|
Reserved |
36Ch-
|
|||
|
Optional (3) |
Next Cap |
Cap. Ver. |
PCI Express Extended Capability - VC |
3C0h |
|
|
Port VC Capability Register 1 |
3C4h |
||||
|
Port VC Capability Register 2 |
3C8h |
||||
|
Port VC Status |
Port VC Control |
3CCh |
|||
|
VC Resource Capability Register 0 |
3D0h |
||||
|
VC Resource Control Register 0 |
3D4h |
||||
|
VC Resource Status Register 0 |
3D8h |
||||
|
|
Reserved |
400h-
|
|||
|
Notes: 1. The MSI Capability Structure varies depending on the selections in the Vivado IDE. 2. Reserved for Endpoint configurations (returns 0x00000000 ). 3. The layout of the PCI Express Extended Configuration Space ( 100h - FFFh ) can change dependent on which optional capabilities are enabled. This table represents the Extended Configuration space layout when all optional extended capability structures. 4. Enabled by default if the SR-IOV option is enabled. 5. A detailed description of the MCAP registers and usage can be found in AR 64761 . |
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