Configuration Space - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The PCI configuration space consists of three primary parts, illustrated in the following table. These include:

  • Legacy PCI v3.0 Type 0/1 Configuration Space Header
    • Type 0 Configuration Space Header used by Endpoint applications (see Table 2)
    • Type 1 Configuration Space Header used by Root Port applications (see Table 3)
  • Legacy Extended Capability Items
    • PCIe Capability Item
    • Power Management Capability Item
    • Message Signaled Interrupt (MSI) Capability Item
    • MSI-X Capability Item (optional)
  • PCIe Capabilities
    • Advanced Error Reporting Extended Capability Structure (AER)
    • Alternate Requester ID (ARI) (optional)
    • Device Serial Number Extended Capability Structure (DSN) (optional)
    • Power Budgeting Enhanced
    • Capability Header (PB) (optional)
    • Latency Tolerance Reporting (LTR) (optional)
    • Dynamic Power Allocation (DPA) (optional)
    • Single Root I/O Virtualization (SR-IOV) (optional)
    • Transaction Processing Hints (TPH) (optional)
    • Virtual Channel Extended Capability Structure (VC) (optional)
  • PCIe Extended Capabilities
    • Device Serial Number Extended Capability Structure (optional)
    • Virtual Channel Extended Capability Structure (optional)
    • Advanced Error Reporting Extended Capability Structure (optional)
    • Media Configuration Access Port (MCAP) Extended Capability Structure (optional)

The core implements up to four legacy extended capability items.

For more information about enabling this feature, see Customizing and Generating the Core.

The core can implement up to ten PCI Express Extended Capabilities. The remaining PCI Express Extended Capability Space is available for users to implement. The starting address of the space available to users begins at 480h. If you choose to implement registers in this space, you can select the starting location of this space, and this space must be implemented in the user application.

For more information about enabling this feature, see Extended Capabilities 1 and Extended Capabilities 2.

Table 1. Common PCI Configuration Space Header
31 16 15 0
Device ID Vendor ID 000h
Status Command 004h
Class Code Rev ID 008h
BIST Header Lat Timer Cache Ln 00Ch

Header Type Specific

(see Table 2 and Table 1)

010h
014h
018h
01Ch
020h
024h
028h
02Ch
030h
CapPtr 034h
038h
Intr Pin Intr Line 03Ch
Reserved 040h-07Ch
PM Capability NxtCap PM Cap 080h
Data Reserved PMCSR 084h
Reserved 088h-08Ch
Customizable MSI Control NxtCap MSI Cap 090h
Message Address (Lower) 094h
Message Address (Upper) 098h
Reserved Message Data 09Ch
Mask Bits 0A0h
Pending Bits 0A4h
Reserved 0A8h-0ACh
Optional MSl-X Control NxtCap MSl-X Cap 0B0h
Table Offset Table BIR 0B4h
PBA Offset PBA BIR 0B8h
Reserved 0BCh
PE Capability NxtCap PE Cap 0C0h
PCI Express Device Capabilities 0C4h
Device Status Device Control 0C8h
PCI Express Link Capabilities 0CCh
Link Status Link Control 0D0h
Root Port Only Slot Capabilities 0D4h
Slot Status Slot Control 0D8h
Root Capabilities Root Control 0DCh
Root Status 0E0h
PCI Express Device Capabilities 2 0E4h
Device Status 2 Device Control 2 0E8h
PCI Express Link Capabilities 2 0ECh
Link Status 2 Link Control 2 0F0h
Unimplemented Configuration Space(Returns 0x00000000 ) 0F4h-0FCh
Always Enabled Next Cap Cap. Ver. PCI Express Extended Cap. ID (AER) 100h
Uncorrectable Error Status Register 104h
Uncorrectable Error Mask Register 108h
Uncorrectable Error Severity Register 10Ch
Correctable Error Status Register 110h
Correctable Error Mask Register 114h
Advanced Error Cap. and Control Register 118h
Header Log Register 1 11Ch
Header Log Register 2 120h
Header Log Register 3 124h
Header Log Register 4 128h
Reserved 12Ch
Optional, Root Port only Root Error Command Register 130h
Root Error Status Register 134h
Error Source ID Register 138h
Reserved 13Ch
Optional Next Cap Cap. Ver. PCI Express Extended Capability - Alternate Requester ID (ARI) 140h
Control Next Function Function Groups 144h
Reserved 148h-14Ch
Optional Next Cap Cap. Ver. PCI Express Extended Capability - DSN 150h
PCI Express Device Serial Number (1st) 154h
PCI Express Device Serial Number (2nd) 158h
Reserved 15Ch
Optional Next Cap Cap. Ver. PCI Express Extended Capability - Power Budgeting Enhanced Capability Header 160h
Reserved DS 164h
Reserved Power Budget Data - State D0, D1, D3, ... 168h
Power Budget Capability 16Ch
Reserved 170h-1B4h
Optional Next Cap Cap. Ver. PCI Express Extended Capability ID - Latency Tolerance Reporting (LTR) 1B8h
No-Snoop Snoop 1BCh
Optional Next Cap Cap. Ver. PCI Express Extended Capability ID - Dynamic Power Allocation 1C0h
Capability Register 1C4h
Latency Indicator 1C8h
Control Status 1CCh
Power Allocation Array Register 0 1D0h
Power Allocation Array Register 1 1D4h
Reserved 1D8h-1FCh
Optional Next Cap Cap. Ver. PCI Express Extended Capability ID - Single Root I/O Virtualization (SR-IOV) 200h
Capability Register 204h
SR-IOV Status (not supported) Control 208h
Total VFs Initial VFs 20Ch
Function Dependency Link Number VFs 210h
VF Stride First VF Offset 214h
VF Device ID Reserved 218h
Supported Page Sizes 21Ch
System Page Size 220h
VF Base Address Register 0 224h
VF Base Address Register 1 228h
VF Base Address Register 2 22Ch
VF Base Address Register 3 230h
VF Base Address Register 4 234h
VF Base Address Register 5 238h
Reserved 23Ch
Reserved 240h-270h
Optional Next Cap Cap. Ver. PCI Express Extended Capability ID - Transaction Processing Hints (TPH) 274h
Capability Register 278h
Requester Control Register 27Ch
Reserved Steering Tag Upper Steering Tag Lower 280h
Reserved 284h - 2FCh
Optional Next Cap Cap. Ver. PCI Express Extended Capability ID - Secondary PCIe Extended Capability 300h
Lane Control (not supported) 304h
Reserved Lane Error Status 308h
Lane Equalization Control Register 0 30Ch
Lane Equalization Control Register 1 310h
Lane Equalization Control Register 2 314h
Lane Equalization Control Register 3 318h
Reserved 31Ch-33Ch
Optional Next Cap Cap. Ver. PCI Express Extended Capability ID - MCAP 340h
Capability Register 344h
FPGA JTAG ID 348h
FPGA Bitstream Version 34Ch
Status Register 350h
Control Register 354h
Data Write Register 358h
Read Data 0 Register 35Ch
Read Data 1 Register 360h
Read Data 2 Register 364h
Read Data 3 Register 368h
Reserved 36Ch-3BCh
Optional Next Cap Cap. Ver. PCI Express Extended Capability - VC 3C0h
Port VC Capability Register 1 3C4h
Port VC Capability Register 2 3C8h
Port VC Status Port VC Control 3CCh
VC Resource Capability Register 0 3D0h
VC Resource Control Register 0 3D4h
VC Resource Status Register 0 3D8h
Reserved 400h-FFFh
The MSI Capability Structure varies depending on the selections in the AMD Vivado™ IDE.
Table 2. Type 0 PCI Configuration Space Header
31 16 15 0  
Device ID Vendor ID 00h
Status Command 04h
Class Code Rev ID 08h
BIST Header Lat Timer Cache Ln 0Ch
Base Address Register 0 10h
Base Address Register 1 14h
Base Address Register 2 18h
Base Address Register 3 1Ch
Base Address Register 4 20h
Base Address Register 5 24h
Cardbus CIS Pointer 28h
Subsystem ID Subsystem Vendor ID 2Ch
Expansion ROM Base Address 30h
Reserved CapPtr 34h
Reserved 38h
Max Lat Min Gnt Intr Pin Intr Line 3Ch
Table 3. Type 1 PCI Configuration Space Header
31 16 15 0  
Device ID Vendor ID 00h
Status Command 04h
Class Code Rev ID 08h
BIST Header Lat Timer Cache Ln 0Ch
Base Address Register 0 10h
Base Address Register 1 14h
Second Lat Timer Sub Bus Number Second Bus Number Primary Bus Number 18h
Secondary Status I/O Limit I/O Base 1Ch
Memory Limit Memory Base 20h
Prefetchable Memory Limit Prefetchable Memory Base 24h
Prefetchable Base Upper 32 Bits 28h
Prefetchable Limit Upper 32 Bits 2Ch
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits 30h
Reserved CapPtr 34h
Expansion ROM Base Address 38h
Bridge Control Intr Pin Intr Line 3Ch