This Figure illustrates the signals associated with the completer request interface of the core. The core delivers each TLP on this interface as an AXI4-Stream packet. The packet starts with a 128-bit descriptor, followed by data in the case of TLPs with a payload.
The completer request interface supports two distinct data alignment modes. In the Dword-aligned mode, the first byte of valid data appears in lane n = (16 + A mod 4) mod w , where:
• A is the byte-level starting address of the data block being transferred
• w is the width of the interface in bytes
In the address-aligned mode, the data always starts in a new beat after the descriptor has ended, and its first valid byte is on lane n = A mod w , where w is the width of the interface in bytes. For memory, I/O, and Atomic Operation requests, address A is the address contained in the request. For messages, the address is always taken as 0 for the purpose of determining the alignment of its payload.