s_axis_tx_tstrb - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

Table: Requester Request Interface Signals for m_axis_rx_tuser shows the Requester Request interface signals used to generate the s_axis_tx_tstrb signal bus.

Table A-14: Requester Request Interface Signals for m_axis_rx_tuser

AXI4-Stream Requester (Enhanced) Request Interface Name

Mnemonic

s_axis_rq_tkeep

s_axis_rq_tuser[3:0]

first_be [3:0]

s_axis_rq_tuser[7:4]

last_be [3:0]

Table: Mapping Between s_axis_cc_tkeep and s_axis_tx_tstrb shows the mapping between s_axis_cc_tkeep from the Completer Completion interface and the s_axis_tx_tstrb signal bus from the AXI4-Stream (Basic) Transmit interface when tlast is not asserted.

Table A-15: Mapping Between s_axis_cc_tkeep and s_axis_tx_tstrb

Interface Width

s_axis_tx_tstrb

s_axis_rq_tkeep

64

0x0F

0x1

0xFF

0x3

128

0x0F

0x1

0xFF

0x3

0xFFF

0x7

0xFFFF

0xF