Stacked Silicon Interconnect (SSI) Devices - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

When SSI devices are used, the PCI Express hard block and the GTH quads connected to the PCIe hard block must be on the same Super Logic Region (SLR).

This Figure shows the XCVU125 device in an A2377 package. Notice that the integrated block for PCIe located at location Y2 cannot select the GTH at bank 228, because an SLR boundary would be crossed.

Figure A-2: XCVU125 Device in an A2377 Package

X-Ref Target - Figure A-2

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