m_axis_rx_tuser - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

Table: RC Interface Signals for m_axis_rx_tuser shows the Requester Completion interface signals used to generate the m_axis_rx_tuser signal bus.

Table A-9: RC Interface Signals for m_axis_rx_tuser

AXI4-Stream Receive
Interface Name

Mnemonic

AXI4-Stream Completer
Request Interface Name

Mnemonic

Notes

m_axis_rx_tuser[0]

rx_ecrc_err

m_axis_rc_tuser[41]

Discontinue

Not exact equivalent

m_axis_rx_tuser[1]

rx_err_fwd

m_axis_rx_tdata[46]

Poisoned
completion

Valid only when Descriptor is present on the data bus (is_sof0/is_sof1=1).

m_axis_rx_tuser[9:2]

rx_bar_hit[7:0]

N/A (Refer to CQ
interface)

N/A

N/A

m_axis_rx_tuser[14:10]

(128-bit only)

rx_is_sof[4:0]

m_axis_rc_tuser[32]

m_axis_rc_tuser[33]

(only for 256-bit straddle)

is_sof_0

is_sof_1

256-bit RC interface provides straddling option. If enabled, the core can straddle two completion TLPs in the same beat.

is_sof_1 is used only when straddling is enabled for 256-bit interface.

m_axis_rx_tuser[21:17]

(128-bit only)

rx_is_eof [4:0]

m_axis_rc_tuser[37:34]

m_axis_rx_tuser[41:38]

(only for 256-bit straddle)

Is_eof_0[3:0]

Is_eof_1[3:0]

is_eof_1 is used only when straddling is enabled for 256-bit interface.

No equivalent signal

m_axis_rc_tuser[74:43]

Parity