GT Channel DRP - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

When checked, enables the GT channel DRP interface.

The signals shown in the following table are available when GT Channel DRP parameter is enabled.

Table 1. GT DRP Ports
Name Direction Width Description
ext_ch_gt_drpaddr I

No Of Lanes x 10

GT Wizard DRP address
ext_ch_gt_drpen I

No Of Lanes x 1

GT Wizard DRP enable
ext_ch_gt_drpdi I

No Of Lanes x 16

GT Wizard DRP data in
ext_ch_gt_drpdo O

No Of Lanes x 16

GT Wizard DRP data out
ext_ch_gt_drprdy O

No Of Lanes x 1

GT Wizard DRP ready
ext_ch_gt_drpwe I

No Of Lanes x 1

GT Wizard DRP write/read