Avoiding Head-of-Line Blocking for Posted Requests - 4.4 English

The integrated block can hold a Non-Posted request received on its RQ interface for lack of transmit credit or lack of available tags. This could potentially result in head-of-line (HOL) blocking for Posted transactions. The integrated block provides a mechanism for the user logic to avoid this situation through these signals:

• pcie_tfc_nph_av[1:0] : These outputs indicate the Header Credit currently available for Non-Posted requests, where:

° 00 = no credit available

° 01 = 1 credit

° 10 = 2 credits

° 11 = 3 or more credits

• pcie_tfc_npd_av[1:0] : These outputs indicate the Data Credit currently available for Non-Posted requests, where:

° 00 = no credit available

° 01 = 1 credit

° 10 = 2 credits

° 11 = 3 or more credits

The user logic can optionally check these outputs before transmitting Non-Posted requests. Because of internal pipeline delays, the information on these outputs is delayed by two user clock cycles from the cycle in which the last byte of the descriptor is transferred on the RQ interface. Thus, the user logic must adjust these values, taking into account any Non-Posted requests transmitted in the two previous clock cycles. This Figure illustrates the operation of these signals for the 256-bit interface. In this example, the integrated block initially had three Non-Posted Header Credits and two Non-Posted Data Credits, and had three free tags available for allocation. Request 1 from the user application had a one-Dword payload, and therefore consumed one header and data credit each, and also one tag. Request 2 in the next clock cycle consumed one header credit, but no data credit. When the user application presents Request 3 in the following clock cycle, it must adjust the available credit and available tag count by taking into account requests 1 and 2. If Request 3 consumes one header credit and one data credit, both available credits are 0 two cycles later, as also the number of available tags.

This Figure and This Figure illustrate the timing of the credit and tag available signals for the same example, for interface width of 128 bits and 64 bits, respectively.