This section demonstrates the Vivado tool flow from start to finish when targeting the VCU108 reference board. Paths and pointers within this flow description assume the default component name pcie3_ultrascale_0 is used.
1. Whe n creating a new Vivado project , selec t a supported p a r t/pa c kage s hown in Table: Tandem PROM/PCIe Supported Configurations .
2. In the Vivado IP catalog, expand Standard Bus Interfaces > PCI Express , and double-click UltraScale FPGA Gen3 Integrated Block for PCI Express to open the Customize IP dialog box.
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X-Ref Target - Figure 3-9 
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3. In the Customize IP dialog box Basic tab, ensure the following options are selected:
° Mode: Advanced
° PCIe Block Location: X0Y0
Note: Use the required PCIe Block Location for the device targeted, as listed in Table: Tandem PROM/PCIe Supported Configurations .
° Tandem Configuration or Dynamic Function eXchange: Tandem
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X-Ref Target - Figure 3-10 
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4.
The example design software attaches to the device through the Vendor ID and Device ID. The Vendor ID must be
16'h10EE
and the Device ID must be
16'h
8038
.
In the
PF0 IDs
tab, set:
° Vendor ID: 10EE
° Device ID: 8038
Note: An alternative solution is the Vendor ID and Device ID can be changed, and the driver and host PC software updated to match the new values.
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X-Ref Target - Figure 3-11 
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5. Perform additional PCIe customizations, and select OK to generate the core.
After core generation, the core hierarchy is available in the Sources tab in the Vivado IDE.
6. In the Sources tab, right-click the core, and select Open IP Example Design .
A new instance of Vivado is created and the example design project automatically loads in the Vivado IDE.
7. Run Synthesis and Implementation.
Click Run Implementation in the Flow Navigator. Select OK to run through synthesis first. The design runs through the complete tool flow, and the end result is a fully routed design supporting Tandem PCIe.
8. Setup PROM or Flash settings, and request two explicit bit files.
Set the appropriate settings to correctly generate a bitstream for a PROM or flash memory device by:
° modifying the constraints in the PCIe IP constraint file (e.g. pcie3_ultrascale_0_tandem ).
° requesting two explicit bitstreams by setting these properties, as seen in the example design constraint file:
set_property HD.OVERRIDE_PERSIST FALSE [current_design]
set_property HD.TANDEM_BITSTREAMS Separate [current_design]
Other values for HD.TANDEM_BITSTREAMS are Combined (default), which is used for the Tandem PROM solution, and None, which generates a standard single-stage bitstream for the entire device. For more information, see Programming the Device .
9. Generate the bitstream.
After Synthesis and Implementation are complete, click Generate Bitstream in the Flow Navigator. The following two files are created and placed in the runs directory:
xilinx_pcie3_uscale_ep_tandem1.bit|
xilinx_pcie3_uscale_ep_tandem2.bit
10. Generate the PROM file for the stage 1.
Run the following command in the Vivado Tcl Console to create a PROM file supported on the VCU108 development board.
write_cfgmem -format mcs -interface BPI -size 256 -loadbit “up 0x0 xilinx_pcie3_uscale_ep_tandem1.bit” xilinx_pcie3_uscale_ep_tandem1.mcs