The simple PIO design generated with the IP represents the
required design structure for Tandem with Field Updates. The top-level design file,
xilinx_pcie_uscale_ep.v, declares the top level pin list and
instantiates pcie3_ultrascale_0 (the IP) and pcie_app_uscale
(everything else). These two submodules are tagged with the HD.TANDEM and HD.RECONFIGURABLE
properties, respectively, to instruct the implementation tools to follow both sets of rules
during place and route.
The following figure shows the basic hierarchy of a Tandem with Field Updates design. The stage 1 bitstream is the pink module only, with stage 2 being comprised of the yellow and white. The partial bitstreams are constructed of the yellow module. The names of the hierarchical instances from the sample design are shown.
Because the vast majority of the design must be placed in a
Reconfigurable Partition, this vast majority must reside in the
pcie_app_uscale hierarchical tree. This includes everything except any I/O
and I/O logic that is located in bank 65 alongside the PCIe IP PERSTN pin. All
user I/O buffers and logic, clocks, GTs and everything else must be in this level of
hierarchy, so it can be swapped for the new version when ready. This requirement means that
designs with IP that contain embedded I/Os that must be placed in bank 65 should not be
considered for Tandem with Field Updates. Manual extraction of these I/Os would be necessary
and is difficult to manage.
The three partitions in the design (Top, PCIe
IP, and User Application) are all synthesized separately, with the two submodules marked
out-of-context. This ensures the separate pieces are not optimized across boundaries, which
would prevent the ability to swap these blocks for implementation. Any synthesis tool can be
used, so long as automatic I/O insertion is disabled. With Vivado synthesis,
this is done by selecting the -mode out_of_context option. Implementation of
each version is done with the entire design in context. From the second version onward, the
place and route results of the PCIe IP and the minimal top-level logic is
locked so it cannot change.