The UltraScale Devices Gen3 Integrated Block for PCIe core can be configured to use 100 MHz, 125 MHz, or 250 MHz reference clock. For more information, see the Answer Records at the AMD PCI Express Solution Center .
The following applies:
• The reference clock can be synchronous or asynchronous with up to ±300 PPM or 600 PPM worst case. (If spread spectrum clock (SSC) is enabled, the link must be synchronous.)
• The PCLK is the primary clock for the PIPE interface.
• In addition to PCLK, two other clocks (CORECLK and USERCLK) are required to support the core.
• BUFG_GTs are used to generate these clocks. These clocks are all driven from the TXOUTCLK pin which is a derived clock from GTREFCLK0 through a CPLL. In an application where QPLL is used, QPLL is only provided to the GT PCS/PMA block while TXOUTCLK continues to be derived from a CPLL.
• The source of the UltraScale GTH reference clock must come directly from IBUFDS_GTE3 .
• To use the reference clock for FPGA general interconnect, another BUFG_GT must be used.
This Figure shows an x2 PCIe clocking architecture example.
In a typical PCI Express solution, the PCI Express reference clock is a spread spectrum clock (SSC), provided at 100 MHz. In most commercial PCI Express systems, SSC cannot be disabled. For more information regarding SSC and PCI Express, see Section 4.3.7.1.1 of the PCI Express Base Specification, rev. 3.0 [Ref 2] .
IMPORTANT: All add-in card designs must use synchronous clocking due to the characteristics of the provided reference clock . For devices using the Slot clock, the Slot Clock Configuration setting in the Link Status register must be enabled in the Vivado ™ IP catalog.
Each link partner device shares the same clock source. This Figure and This Figure show a system using a 100 MHz reference clock. Even if the device is part of an embedded system, if the system uses commercial PCI Express root complexes or switches along with typical motherboard clocking schemes, synchronous clocking should still be used.
Note: This Figure and This Figure are high-level representations of the board layout. Ensure that coupling, termination, and details are correct when laying out a board. See Board Design Guidelines in the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 12] .
Starting 2017.1, the PCIe core checks for GT power to be stable before the clock is enabled.
• This results in a logic driven CE (rather than VCC) for the BUFG_GT that is driven by IBUFDS_GTE4 (PCIe ref clock).
• Before this change in CE, if you had another (parallel) BUFG_GT connected to the IBUFDS_GTE4 with CE driven by VCC, the BUFG_GT_SYNC inserted by opt_design/MLO could drive both BUFG_GTs.
• If there is a parallel BUFG_GT that does not share the same CE as the PCIe BUFG_GT clock, then two BUFG_GT_SYNC are inserted by opt_design/MLO.
• Because you can only have one BUFG_GT_SYNC for IBUFDS_GTE4 driven BUFG_GTs, the router does not know how to handle the second BUFG_GT_SYNC and does not route the IBUFDS_GTE4/ODIV2 driven clock net.
• You must ensure that the BUFG_GTs driven by the IBUFDS_GTE4 have the same CE/CLR pins.