SRIOV Base Address Register Overview - 4.4 English - PG156

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

In Endpoint configuration, the core supports up to six 32-bit BARs or three 64-bit BARs. In Root Port configuration, the core supports up to two 32-bit BARs or one 64-bit BAR. SRIOV BARs can be one of two sizes:

32-bit BARs
The address space can be as small as 16 bytes or as large as 2 Gbytes. Used for memory to I/O.
64-bit BARs
The address space can be as small as 128 bytes or as large as 256 gigabytes. Used for memory only.

All SRIOV BAR registers have these options:

Checkbox
Click the checkbox to enable the BAR; deselect the checkbox to disable the BAR.
Type
SRIOV BARs can either be I/O or Memory.
I/O
I/O BARs can only be 32-bit; the Prefetchable option does not apply to I/O BARs. I/O BARs are only enabled for the Legacy PCI Express Endpoint core.
Memory
Memory BARs can be either 64-bit or 32-bit and can be prefetchable. When a BAR is set as 64 bits, it uses the next BAR for the extended address space and makes the next BAR inaccessible.
Size
The available size range depends on the PCIe device/port type and the type of BAR selected. The following table lists the available BAR size ranges.
Table 1. SRIOV BAR Size Ranges for Device Configuration
PCIe Device / Port Type BAR Type BAR Size Range
PCI Express Endpoint 32-bit Memory 128 bytes – 2 gigabytes
64-bit Memory 128 bytes – 256 gigabytes
Legacy PCI Express Endpoint 32-bit Memory 16 bytes – 2 gigabytes
64-bit Memory 16 bytes – 256 gigabytes
I/O 16 bytes – 2 gigabytes
Prefetchable
Identifies the ability of the memory space to be prefetched.
Value
The value assigned to the BAR based on the current selections.

For more information about managing the SRIOV Base Address Register settings, see Managing Base Address Register Settings.