See the cfg_interrupt_msi * and
cfg_interrupt_msix_ * descriptions in Configuration Interrupt Controller Interface.
The integrated block core supports sending interrupt requests as either legacy, Message MSI, or MSI-X interrupts. The mode is programmed using the MSI Enable bit in the Message Control register of the MSI Capability Structure and the MSI-X Enable bit in the MSI-X Message Control register of the MSI-X Capability Structure. For more information on the MSI and MSI-X capability structures, see section 6.8 of the PCI Local Base Specification v3.0.
The state of the MSI Enable and MSI-X Enabled bits is
reflected by the cfg_interrupt_msi_enable and
cfg_interrupt_msix_enable outputs, respectively. The following table
describes the Interrupt Mode to which the device has been programmed, based on the
cfg_interrupt_msi_enable and cfg_interrupt_msix_enable
outputs of the core.
| cfg_interrupt_msixenable=0 | cfg_interrupt_msixenable=1 | |
|---|---|---|
| cfg_interrupt_ msi_enable=0 |
Legacy Interrupt (INTx) mode. The cfg_interrupt interface only sends INTx messages. |
MSI-X mode. MSI-X interrupts can be generated using the
|
| cfg_interrupt_ msi_enable=1 | MSI mode. The cfg_interrupt interface only sends MSI interrupts (MWr TLPs). |
Undefined. System software is not supposed to permit this.
However, the |
The MSI Enable bit in the MSI control register, the MSI-X Enable bit in the MSI-X Control register, and the Interrupt Disable bit in the PCI Command register are programmed by the Root Complex. The user application has no direct control over these bits.
The Internal Interrupt Controller in the core only generates
Legacy Interrupts and MSI Interrupts. MSI-X Interrupts need to be generated by the user
application and presented on the transmit AXI4-Stream interface. The status of
cfg_interrupt_msi_enable determines the type of interrupt generated by the
internal Interrupt Controller:
If the MSI Enable bit is set to a 1, then the core generates MSI
requests by sending Memory Write TLPs. If the MSI Enable bit is set to 0, the
core generates legacy interrupt messages as long as the Interrupt Disable bit in the PCI
Command register is set to 0.
-
cfg_interrupt_msi_enable=0: Legacy interrupt -
cfg_interrupt_msi_enable=1: MSI - Command register bit 10 =
0: INTx interrupts enabled - Command register bit 10 =
1: INTx interrupts disabled (requests are blocked by the core)
The user application can monitor
cfg_function_status to check whether INTx interrupts are enabled or
disabled. For more information, see Configuration Status Interface.
The user application requests interrupt service in one of two ways, each of which are described in the following section.