Enable In System IBERT - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2023-11-24
Version
4.4 English

This debug option is used to check and see the eye diagram of the serial link at the desired link speed. For more information on In System IBERT, see In-System IBERT LogiCORE IP Product Guide (PG246) [Ref 24] .

IMPORTANT: This option is used mainly for hardware debug purposes. Simulations are not supported when this option is used.

Steps to check the eye diagram:

1. Select a suitable AMD reference board.

2. Configure the core with the following options:

° Select the Gen3, Gen2 or Gen1 link speed at any link width.

° Select the Enable In System IBERT option in the Add. Debug Options page.

3. Open the Example Design.

4. Generate a .bit file and .ltx file.

5. Open Hardware Manger (HM) and configure the FPGA using the generated .bit and .ltx file.

6. Reboot the machine to rescan and to run the enumeration process again.

7. Select the Serial I/O links tab at the bottom of the HM, and create links for the scan window.

8. Select any one of the links in Serial I/O links tab, and right-click and choose scan link option.

9. For better results try Horizontal and Vertical increment by 2 instead the default value.

10. After the eye scan is selected, the eye diagram will be plotted.

IMPORTANT: Enable In System IBERT should not be used with the Falling Edge Receiver Detect option in GT Settings tab.