In both Dword-aligned, the transfer starts with the sixteen descriptor bytes, followed immediately by the payload bytes. The user application must keep the s_axis_rq_tvalid signal asserted over the duration of the packet. The integrated block treats the deassertion of s_axis_rq_tvalid during the packet transfer as an error, and nullifies the corresponding Request TLP transmitted on the link to avoid data corruption.
The user application must also assert the s_axis_rq_tlast signal in the last beat of the packet. The integrated block can deassert s_axis_rq_tready in any cycle if it is not ready to accept data. The user application must not change the values on the RQ interface during cycles when the integrated block has deasserted s_axis_rq_tready . The AXI4-Stream interface signals s_axis_rq_tkeep (one per Dword position) must be set to indicate the valid Dwords in the packet including the descriptor and any null bytes inserted between the descriptor and the payload. That is, the tkeep bits must be set to 1 contiguously from the first Dword of the descriptor until the last Dword of the payload. During the transfer of a packet, the tkeep bits can be 0 only in the last beat of the packet, when the packet does not fill the entire width of the interface.
The requester request interface also includes the First Byte Enable and the Last Enable bits in the s_axis_rq_tuser bus. These must be set in the first beat of the packet, and provide information of the valid bytes in the first and last Dwords of the payload.
The user application must limit the size of the payload transferred in a single request to the maximum payload size configured in the integrated block, and must ensure that the payload does not cross a 4 Kbyte boundary. For memory writes of two Dwords or less, the 1s in first_be and last_be can be non-contiguous. For the special case of a zero-length memory write request, the user application must provide a dummy one-Dword payload with first_be and last_be both set to all 0s. For memory writes and reads of one DW transfers, last_be should be 0 and bits in first_be indicate valid bytes. In all other cases, the 1 bits in first_be and last_be must be contiguous.
The timing diagrams in This Figure , This Figure , and This Figure illustrate the Dword-aligned transfer of a memory write request from the user application across the requester request interface, when the interface width is configured as 64, 128, and 256 bits, respectively. For illustration purposes, the size of the data block being written into user application memory is assumed to be n Dwords, for some n = k × 32 + 29, k > 0.
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The timing diagrams in This Figure , This Figure , and This Figure illustrate the address-aligned transfer of a memory write request from the user application across the RQ interface, when the interface width is configured as 64, 128, and 256 bits, respectively. For illustration purposes, the starting Dword offset of the data block being written into user application memory is assumed to be ( m × 32 + 1), for some integer m > 0. Its size is assumed to be n Dwords, for some n = k × 32 + 29, k > 0.
In the address-aligned mode, the delivery of the payload always starts in the beat following the last byte of the descriptor. The first Dword of the payload can appear at any Dword position. The user application must communicate the offset of the first Dword of the payload on the datapath using the addr_offset[2:0] signal in s_axis_rq_tuser . The user application must also set the bits in first_be[3:0] to indicate the valid bytes in the first Dword and the bits in last_be[3:0] to indicate the valid bytes in the last Dword of the payload.
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