Maximum Link Speed - 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

Document ID
PG156
Release Date
2024-12-06
Version
4.4 English

The core allows you to select the Maximum Link Speed supported by the device. The following table defines the lane widths and link speeds supported by the device. Higher link speed cores are capable of training to a lower link speed if connected to a lower link speed capable device.

Table 1. Lane Width and Link Speed
Lane Width Link Speed
x8 8 Gb/s