In Endpoint configuration, the core supports up to six 32-bit BARs or three 64-bit BARs, and the Expansion read-only memory (ROM) BAR. In Root Port configuration, the core supports up to two 32-bit BARs or one 64-bit BAR, and the Expansion ROM BAR.
BARs can be one of two sizes:
• 32-bit BARs: The address space can be as small as 128 bytes or as large as 2 gigabytes. Used for Memory to I/O.
• 64-bit BARs: The address space can be as small as 128 bytes or as large as 256 gigabytes . Used for Memory only.
All BAR registers share these options:
• Checkbox: Click the checkbox to enable the BAR; deselect the checkbox to disable the BAR.
• Type: BARs can either be I/O or Memory.
° I/O : I/O BARs can only be 32-bit; the Prefetchable option does not apply to I/O BARs. I/O BARs are only enabled for the Legacy PCI Express Endpoint core.
° Memory : Memory BARs can be either 64-bit or 32-bit and can be prefetchable. When a BAR is set as 64 bits, it uses the next BAR for the extended address space and makes the next BAR inaccessible.
• Size: The available Size range depends on the PCIe Device/Port Type and the Type of BAR selected. Table: BAR Size Ranges for Device Configuration lists the available BAR size ranges.
• Prefetchable: Identifies the ability of the memory space to be prefetched.
• Value: The value assigned to the BAR based on the current selections.
For more information about managing the Base Address Register settings, see Managing Base Address Register Settings .