Example Design Elements - 4.4 English

The PIO example design elements include:

• Core wrapper

• An example Verilog HDL wrapper (instantiates the cores and example design)

• A customizable demonstration test bench to simulate the example design

The example design has been tested and verified with Vivado Design Suite and these simulators:

• Vivado simulator

• Mentor Graphics QuestaSim

• Cadence Incisive Enterprise Simulator (IES)

• Synopsys Verilog Compiler Simulator (VCS)

For the supported versions of these tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing ⁽²⁾ .