These considerations are critical for safe and reliable operation of the target device.
• When using Tandem PCIe, the stage 1 and stage 2 bitstreams must remain linked together. The stage 2 bitstream must always be the one created with the stage 1 bitstream delivered from flash. You cannot follow a stage 1 bitstream with a partial or clearing bitstream, or a stage 2 bitstream created from a different implementation result of a design even if Field Updates is selected.
• Always be sure that the partial and clearing bitstreams are compatible with the current static design in the FPGA before loading them. PR_Verify is a fundamental part of the Dynamic Function eXchange solution and must be used for Tandem with Field Updates for the same reason. PR_Verify confirms that multiple design configurations (i.e., versions) are compatible with each other and therefore safe to overlay in hardware.
• The initial Tandem configuration of the device must be done with a bitstream set compiled as a version within a Tandem with Field Updates flow. If the initial bitstream load has been done with a standard Tandem bitstream set, it will not be compatible with later Field Update clearing or partial bitstreams. Contention could occur and device damage is possible.