The second difference is the design structure. In order to swap one user application from one version to the next, it must be completely enclosed within its own level of hierarchy. The interface of this instantiation cannot change; otherwise, the top-level static design needs to be recompiled. Everything other than the UltraScale Devices Gen3 Integrated Block for PCIe core (in its own level of hierarchy below top) and any I/O logic (buffers, MMCM, PLL, XiPhy, etc.) that are placed in bank 65 are in this level of hierarchy (and below). This means that all I/O logic for all other banks must be placed here and not inferred at the top level, so instantiation of I/O buffers is required.
TIP: To see a simple example of this design structure, generate an example design while targeting the KCU105 demo board.
Another requirement of the design structure is that all elements to be placed in the configuration frame must also be part of this top-level design (or another level of hierarchy separate from the PCIe IP and the user application. These elements include the BSCAN, ICAP, STARTUP , FRAME_ECC and related components (see Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) [Ref 19] for the complete list), and they must be hierarchically isolated because they are not permitted to be dynamically reconfigured. The implications of this mean that IP cores that require these elements, such as the Vivado Debug Hub and the Memory Interface Generator (MIG), which both use BSCAN, must take special precautions to be safely implemented. For details, see Debugging Tandem with Field Updates Designs .
All other considerations for Tandem Configuration are still applicable for Tandem with Field Updates when working with UltraScale devices . For example, PERSIST must be used for Tandem PROM, and stage 1 must remain linked to stage 2 from the same implementation result. Reconfigurable Stage Twos, the feature that allows you to pair new stage 2 bitstreams with a given stage 1 as well as the ability to dynamically reconfigure with stage 2 bitstreams, this is only supported for UltraScale+ devices.