The UltraScale Devices Gen3 Integrated Block for PCIe solution delivered from the Vivado IP catalog has certain placement restrictions to ensure that your design closes timing. Following are two of the rules that impact the ability of the PCI Express solution to migrate across packages.
• Rule #1 – Lane 0 of the PCIe Interface is limited to the GTH quad one clock region above, in the same clock region or one clock region below the PCI Express hard block. When eight PCI Express lanes are used, the GTH quads must be in adjacent quads.
• Rule #2 – The integrated block for PCIe and the GTH transceivers that are connected together must reside on the same Super Logic Region (SLR).
These two rules are explained in further detail in the following sections.